Fixed issue #13

myhdl/conversion/_toVHDL.py

@@ -1,4 +1,4 @@
-#  This file is part of the myhdl library, a Python package for using
+
 #  Python as a Hardware Description Language.
 #
 #  Copyright (C) 2003-2014 Jan Decaluwe
@@ -906,6 +906,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
         fn = node.func
         # assert isinstance(fn, astNode.Name)
         f = self.getObj(fn)
+        fname = ''
         pre, suf = '', ''
         opening, closing = '(', ')'
         sep = ", "
@@ -974,11 +975,14 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
             opening, closing =  "unsigned'(", ")"
             sep = " & "
         elif hasattr(node, 'tree'):
-            self.write(node.tree.name)
+            pre, suf = self.inferCast(node.vhd, node.tree.vhd)
+            fname = node.tree.name
         else:
             self.write(f.__name__)
         if node.args:
             self.write(pre)
+            # TODO rewrite making use of fname variable
+            self.write(fname)
             self.write(opening)
             self.visit(node.args[0])
             for arg in node.args[1:]:
@@ -1799,6 +1803,7 @@ class _ConvertFunctionVisitor(_ConvertVisitor):
 
     def visit_Return(self, node):
         self.write("return ")
+        node.value.vhd = self.tree.vhd
         self.visit(node.value)
         self.write(";")
 

myhdl/test/bugs/test_issue_13.py

@@ -0,0 +1,41 @@
+from myhdl import *
+from myhdl.conversion import analyze
+
+def issue_13(reset, clk, d, en, q):
+    COSET = 0x55
+
+    def calculateHec(header):
+        """ Return hec for an ATM header, represented as an intbv.
+
+        The hec polynomial is 1 + x + x**2 + x**8.
+        """
+        hec = intbv(0)[8:]
+
+        for ii in downrange(len(header)):
+            bit = header[ii]
+            hec[8:] = concat(hec[7:2],
+                             bit ^ hec[1] ^ hec[7],
+                             bit ^ hec[0] ^ hec[7],
+                             bit ^ hec[7]
+                            )
+        return hec ^ COSET
+
+    @always_seq(clk.posedge, reset=reset)
+    def logic():
+        if en:
+            q.next = calculateHec(d)
+
+    return logic
+
+def test_issue_13():
+
+    reset = ResetSignal(0, active=1, async=False)
+    clk   = Signal(bool(0))
+    d     = Signal(intbv(0)[32:])
+    en    = Signal(bool(0))
+    q     = Signal(intbv(0)[8:])
+
+    # toVHDL.numeric_ports = False
+
+    assert analyze(issue_13, reset, clk, d, en, q) == 0 
+