skip wrongly-placed docstrings

(was fixed automatically with previous committed fix)

myhdl/conversion/_toVHDL.py

@@ -899,7 +899,7 @@ class _ConvertVisitor(_ConversionMixin):
 
     def visitDiscard(self, node, *args):
         expr = node.expr
-        # skip extra semicolons
+        # skip extra semicolons and wrongly-placed docstrings
         if isinstance(expr, astNode.Const):
             return
         self.visit(expr)

myhdl/conversion/_toVerilog.py

@@ -625,7 +625,7 @@ class _ConvertVisitor(_ConversionMixin):
 
     def visitDiscard(self, node, *args):
         expr = node.expr
-        # skip extra semicolons
+        # skip extra semicolons and wrongly-placed docstrings
         if isinstance(expr, astNode.Const):
             return
         self.visit(expr)

myhdl/test/bugs/test_bug_1835797.py

@@ -0,0 +1,32 @@
+import sys
+import os
+path = os.path
+import random
+from random import randrange
+random.seed(2)
+
+from myhdl import *
+from myhdl.conversion import verify
+
+
+ACTIVE_LOW, INACTIVE_HIGH = bool(0), bool(1)
+
+def bug_1835797():
+    """ Docstring in the middle.
+
+    """
+    
+    @instance
+    def logic():
+        v = intbv(0, min=-15, max=45)
+        """Wrongly placed docstring"""
+        yield delay(10)
+        print v.min
+        print v.max
+        
+    return logic
+
+
+def test_bug_1835797():  
+    assert verify(bug_1835797) == 0
+