diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index 7f677642..39575e3c 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -899,7 +899,7 @@ class _ConvertVisitor(_ConversionMixin): def visitDiscard(self, node, *args): expr = node.expr - # skip extra semicolons + # skip extra semicolons and wrongly-placed docstrings if isinstance(expr, astNode.Const): return self.visit(expr) diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py index 499a27cc..3f46291e 100644 --- a/myhdl/conversion/_toVerilog.py +++ b/myhdl/conversion/_toVerilog.py @@ -625,7 +625,7 @@ class _ConvertVisitor(_ConversionMixin): def visitDiscard(self, node, *args): expr = node.expr - # skip extra semicolons + # skip extra semicolons and wrongly-placed docstrings if isinstance(expr, astNode.Const): return self.visit(expr) diff --git a/myhdl/test/bugs/test_bug_1835797.py b/myhdl/test/bugs/test_bug_1835797.py new file mode 100644 index 00000000..c53f6681 --- /dev/null +++ b/myhdl/test/bugs/test_bug_1835797.py @@ -0,0 +1,32 @@ +import sys +import os +path = os.path +import random +from random import randrange +random.seed(2) + +from myhdl import * +from myhdl.conversion import verify + + +ACTIVE_LOW, INACTIVE_HIGH = bool(0), bool(1) + +def bug_1835797(): + """ Docstring in the middle. + + """ + + @instance + def logic(): + v = intbv(0, min=-15, max=45) + """Wrongly placed docstring""" + yield delay(10) + print v.min + print v.max + + return logic + + +def test_bug_1835797(): + assert verify(bug_1835797) == 0 +