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intermediate toVHDL checkin

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This commit is contained in:
jand 2006-06-29 08:10:57 +00:00
parent 5a18828ea6
commit a6b77fd084
5 changed files with 59 additions and 18 deletions
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9
myhdl/_Signal.py
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@ -54,7 +54,8 @@ class _PosedgeWaiterList(_WaiterList):
def _toVerilog(self):
return "posedge %s" % self.sig._name
def _toVHDL(self):
return "rising_edge(%s)" % self.sig._name
return self.sig._name
#return "rising_edge(%s)" % self.sig._name
class _NegedgeWaiterList(_WaiterList):
def __init__(self, sig):
@ -62,7 +63,8 @@ class _NegedgeWaiterList(_WaiterList):
def _toVerilog(self):
return "negedge %s" % self.sig._name
def _toVHDL(self):
return "falling_edge(%s)" % self.sig._name
return self.sig._name
#return "falling_edge(%s)" % self.sig._name
def posedge(sig):
@ -260,7 +262,8 @@ class Signal(object):
# length
def __len__(self):
return len(self._val)
return self._nrbits
# return len(self._val)
# indexing and slicing methods

2
myhdl/_extractHierarchy.py
View File

@ -185,7 +185,7 @@ class _HierExtr(object):
top_inst = hierarchy[0]
obj, subs = top_inst.obj, top_inst.subs
names[id(obj)] = name
absnames[id(obj)] = '_' + name
absnames[id(obj)] = name
for inst in hierarchy:
obj, subs = inst.obj, inst.subs
assert id(obj) in names

22
myhdl/_toVHDL/_convert.py
View File

@ -155,7 +155,7 @@ def _writeModuleHeader(f, intf):
def _writeSigDecls(f, intf, siglist, memlist):
print >> f, "architecture MYHDL of %s is" % intf.name
print >> f, "architecture MyHDL of %s is" % intf.name
print >> f
constwires = []
for s in siglist:
@ -170,7 +170,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
)
# the following line implements initial value assignments
# print >> f, "%s %s%s = %s;" % (s._driven, r, s._name, int(s._val))
print >> f, "signal %s%s %s;" % (p, r, s._name)
print >> f, "signal %s %s%s;" % (s._name, p, r)
elif s._read:
# the original exception
# raise ToVerilogError(_error.UndrivenSignal, s._name)
@ -191,7 +191,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
def _writeModuleFooter(f):
print >> f, "end architecture MYHDL;"
print >> f, "end architecture MyHDL;"
def _writeTestBench(f, intf):
@ -420,7 +420,7 @@ class _ConvertVisitor(_ToVerilogMixin):
assert node.attrname == 'next'
self.isSigAss = True
self.visit(node.expr)
node.obj = self.getObj(node.expr)
def visitAssert(self, node, *args):
# XXX
pass
@ -462,6 +462,8 @@ class _ConvertVisitor(_ToVerilogMixin):
self.isSigAss = False
else:
self.write(' = ')
node.expr.target = self.getObj(node.nodes[0])
print node.expr.target
self.visit(node.expr)
self.write(';')
@ -564,7 +566,17 @@ class _ConvertVisitor(_ToVerilogMixin):
if context == _context.PRINT:
self.write('"%s"' % node.value)
else:
self.write(node.value)
target = self.getTarget(node)
if target is not None:
if isinstance(target, Signal):
if target._type is bool:
self.write("'%s'" % node.value)
elif target._type is intbv:
self.write('"%s"' % bin(node.value, len(target)))
else:
self.write(node.value)
else:
self.write(node.value)
def visitContinue(self, node, *args):
self.write("disable %s;" % self.labelStack[-1])

5
myhdl/_toVerilog/__init__.py
View File

@ -91,6 +91,11 @@ class _ToVerilogMixin(object):
if hasattr(node, 'obj'):
return node.obj
return None
def getTarget(self, node):
if hasattr(node, 'target'):
return node.target
return None
def getKind(self, node):
if hasattr(node, 'kind'):

39
myhdl/_toVerilog/_analyze.py
View File

@ -129,7 +129,7 @@ def _analyzeGens(top, absnames):
s = re.sub(r"@.*", "", s)
s = s.lstrip()
ast = compiler.parse(s)
# print ast
#print ast
ast.sourcefile = inspect.getsourcefile(f)
ast.lineoffset = inspect.getsourcelines(f)[1]-1
ast.symdict = f.func_globals.copy()
@ -142,7 +142,7 @@ def _analyzeGens(top, absnames):
assert isinstance(obj, (int, long, Signal)) or \
_isMem(obj) or isTupleOfInts(obj)
ast.symdict[n] = obj
ast.name = absnames.get(id(g), _Label("BLOCK"))
ast.name = absnames.get(id(g), str(_Label("BLOCK"))).upper()
v = _NotSupportedVisitor(ast)
compiler.walk(ast, v)
if isinstance(g, _AlwaysComb):
@ -157,13 +157,13 @@ def _analyzeGens(top, absnames):
s = re.sub(r"@.*", "", s)
s = s.lstrip()
ast = compiler.parse(s)
# print ast
#print ast
ast.sourcefile = inspect.getsourcefile(f)
ast.lineoffset = inspect.getsourcelines(f)[1]-1
ast.symdict = f.f_globals.copy()
ast.symdict.update(f.f_locals)
ast.callstack = []
ast.name = absnames.get(id(g), _Label("BLOCK"))
ast.name = absnames.get(id(g), str(_Label("BLOCK"))).upper()
v = _NotSupportedVisitor(ast)
compiler.walk(ast, v)
v = _AnalyzeBlockVisitor(ast)
@ -480,8 +480,8 @@ class _AnalyzeVisitor(_ToVerilogMixin):
node.obj = bool()
elif f is int:
node.obj = int()
elif f in (posedge , negedge):
node.obj = _EdgeDetector()
## elif f in (posedge , negedge):
## node.obj = _EdgeDetector()
elif f is delay:
node.obj = delay(0)
elif f in myhdlObjects:
@ -540,10 +540,31 @@ class _AnalyzeVisitor(_ToVerilogMixin):
if n.signed:
node.signed = True
op, arg = node.ops[0]
if op == '==':
if isinstance(node.expr, astNode.Name) and \
isinstance(arg.obj, EnumItemType):
# detect specialized case for the test
if op == '==' and isinstance(node.expr, astNode.Name):
n = node.expr.name
# check wether it can be a case
if isinstance(arg.obj, EnumItemType):
node.case = (node.expr, arg.obj)
# check whether it can be part of an edge check
elif n in self.ast.sigdict:
sig = self.ast.sigdict[n]
if isinstance(arg.obj, astNode.Const):
v = arg.obj.value
if value == 0:
node.edge = sig.negedge
elif value == 1:
node.edge = sig.posedge
elif isinstance(arg.obj, astNode.Name):
c = arg.obj.name
if c in self.ast.symdict:
a = self.ast.symdict[n]
if isinstance(a, int):
if a == 0:
node.edge = sig.negedge
elif a == 1:
node.edge = sig.posedge
def visitConst(self, node, *args):
node.signed = False