Migrate interfaces test; infer interface only after signal analysis

myhdl/_instance.py

@@ -86,7 +86,7 @@ class _Instantiator(object):
             symdict.update(zip(freevars, closure))
         self.symdict = symdict
 
-        print modname, genfunc.__name__
+        # print modname, genfunc.__name__
         tree = self.ast
         # print ast.dump(tree)
         v = _AttrRefTransformer(self)

myhdl/_module.py

@@ -52,6 +52,8 @@ class _Module(object):
 class _ModuleInstance(object):
 
     def __init__(self, mod, *args, **kwargs):
+        self.args = args
+        self.kwargs = kwargs
         self.mod = mod
         self.sigdict = {}
         self.memdict = {}
@@ -59,7 +61,7 @@ class _ModuleInstance(object):
         self.subs = _flatten(mod.modfunc(*args, **kwargs))
         self.verifyMod()
         self.updateMod()
-        self.inferInterface(*args, **kwargs)
+        # self.inferInterface(*args, **kwargs)
         self.name = self.__name__ = mod.__name__ + '_' + str(mod.count)
 
     def verifyMod(self):
@@ -85,8 +87,8 @@ class _ModuleInstance(object):
             self.memdict[n] = m
             m._used = True
 
-    def inferInterface(self, *args, **kwargs):
+    def inferInterface(self):
         from myhdl.conversion._analyze import _analyzeTopFunc
-        intf = _analyzeTopFunc(self.mod.modfunc, *args, **kwargs)
+        intf = _analyzeTopFunc(self.mod.modfunc, *self.args, **self.kwargs)
         self.argnames = intf.argnames
         self.argdict = intf.argdict

myhdl/conversion/_toVHDL.py

@@ -185,7 +185,9 @@ class _ToVHDLConvertor(object):
 
         ### infer interface
         if isinstance(func, _ModuleInstance):
-            intf = func # already inferred
+            # infer interface after signals have been analyzed
+            func.inferInterface()
+            intf = func
         else:
             intf = _analyzeTopFunc(func, *args, **kwargs)
         intf.name = name

myhdl/conversion/_toVerilog.py

@@ -171,7 +171,9 @@ class _ToVerilogConvertor(object):
 
         ### infer interface
         if isinstance(func, _ModuleInstance):
-            intf = func # already inferred
+            # infer interface after signals have been analyzed
+            func.inferInterface()
+            intf = func
         else:
             intf = _analyzeTopFunc(func, *args, **kwargs)
         intf.name = name

myhdl/test/conversion/general/test_interfaces1.py

@@ -12,6 +12,7 @@ class MyIntf(object):
         self.x = Signal(intbv(2,min=0,max=16))
         self.y = Signal(intbv(3,min=0,max=18))
 
+@module
 def m_one_level(clock,reset,ia,ib):
 
     @always_seq(clock.posedge,reset=reset)
@@ -21,6 +22,7 @@ def m_one_level(clock,reset,ia,ib):
 
     return rtl
 
+@module
 def m_two_level(clock,reset,ia,ib):
 
     ic,ie = (MyIntf(),MyIntf(),)
@@ -32,6 +34,7 @@ def m_two_level(clock,reset,ia,ib):
 
     return g_one, rtl
 
+@module
 def c_testbench_one():
     clock = Signal(bool(0))
     reset = ResetSignal(0,active=0,async=True)
@@ -63,6 +66,7 @@ def c_testbench_one():
 
     return tb_dut, tb_clk, tb_stim
 
+@module
 def c_testbench_two():
     clock = Signal(bool(0))
     reset = ResetSignal(0,active=0,async=True)
@@ -99,20 +103,20 @@ def test_one_level_analyze():
     reset = ResetSignal(0,active=0,async=True)
     ia = MyIntf()
     ib = MyIntf()
-    analyze(m_one_level,clock,reset,ia,ib)
+    analyze(m_one_level(clock,reset,ia,ib))
 
 def test_one_level_verify():
-    assert verify(c_testbench_one) == 0
+    assert verify(c_testbench_one()) == 0
 
 def test_two_level_analyze():
     clock = Signal(bool(0))
     reset = ResetSignal(0,active=0,async=True)
     ia = MyIntf()
     ib = MyIntf()
-    analyze(m_two_level,clock,reset,ia,ib)
+    analyze(m_two_level(clock,reset,ia,ib))
 
 def test_two_level_verify():
-    assert verify(c_testbench_two) == 0
+    assert verify(c_testbench_two()) == 0
 
 
 if __name__ == '__main__':