diff --git a/myhdl/_extractHierarchy.py b/myhdl/_extractHierarchy.py
index ffa0923f..97e935d7 100644
--- a/myhdl/_extractHierarchy.py
+++ b/myhdl/_extractHierarchy.py
@@ -46,13 +46,15 @@ _error.InconsistentToplevel = "Inconsistent top level %s for %s - should be 1"
 
 
 class _Instance(object):
-    __slots__ = ['level', 'obj', 'subs', 'sigdict', 'memdict', 'name']
-    def __init__(self, level, obj, subs, sigdict, memdict):
+    __slots__ = ['level', 'obj', 'subs', 'sigdict', 'memdict', 'name', 'func', 'argdict']
+    def __init__(self, level, obj, subs, sigdict, memdict, func, argdict):
         self.level = level
         self.obj = obj
         self.subs = subs
         self.sigdict = sigdict
         self.memdict = memdict
+        self.func = func
+        self.argdict = argdict
         
 
 _memInfoMap = {}
@@ -302,6 +304,11 @@ class _HierExtr(object):
                 if isGenSeq and arg:
                     sigdict = {}
                     memdict = {}
+                    argdict = {} 
+                    if func:
+                        arglist = inspect.getargspec(func).args 
+                    else:
+                        arglist = []
                     cellvars = frame.f_code.co_cellvars
                     for dict in (frame.f_globals, frame.f_locals):
                         for n, v in dict.items():
@@ -319,6 +326,9 @@ class _HierExtr(object):
                                 memdict[n] = m
                                 if n in cellvars:
                                     m._used = True
+                            # save any other variable in argdict
+                            if (n in arglist) and (n not in sigdict) and (n not in memdict):
+                                argdict[n] = v
                                 
                     subs = []
                     for n, sub in frame.f_locals.items():
@@ -326,7 +336,7 @@ class _HierExtr(object):
                             if elt is sub:
                                 subs.append((n, sub))
                                 
-                    inst = _Instance(self.level, arg, subs, sigdict, memdict)
+                    inst = _Instance(self.level, arg, subs, sigdict, memdict, func, argdict)
                     self.hierarchy.append(inst)
                     
                 self.level -= 1
diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
index 2d887879..ed682293 100644
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -180,6 +180,8 @@ class _ToVHDLConvertor(object):
         arch = self.architecture
         numeric = self.numeric_ports
         
+        self._convert_filter(h, intf, siglist, memlist, genlist)
+        
         if pfile:
             _writeFileHeader(pfile, ppath)
             print >> pfile, _package
@@ -201,7 +203,11 @@ class _ToVHDLConvertor(object):
         # tbfile.close()
 
         ### clean-up properly ###
+        self._cleanup(siglist)
+
+        return h.top
         
+    def _cleanup(self, siglist):
         # clean up signal names
         for sig in siglist:
             sig._clear()
@@ -217,8 +223,12 @@ class _ToVHDLConvertor(object):
         self.no_myhdl_package = False
         self.architecture = "MyHDL"
         self.numeric_ports = True
-
-        return h.top
+        
+        
+    def _convert_filter(self, h, intf, siglist, memlist, genlist):
+        # intended to be a entry point for other uses: 
+        #  code checking, optimizations, etc
+        pass
     
 
 toVHDL = _ToVHDLConvertor()
diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py
index 8d5fa4bf..8e3916ae 100644
--- a/myhdl/conversion/_toVerilog.py
+++ b/myhdl/conversion/_toVerilog.py
@@ -137,6 +137,8 @@ class _ToVerilogConvertor(object):
         intf = _analyzeTopFunc(func, *args, **kwargs)
         intf.name = name
         doc = _makeDoc(inspect.getdoc(func))
+        
+        self._convert_filter(h, intf, siglist, memlist, genlist)
 
         _writeFileHeader(vfile, vpath, self.timescale)
         _writeModuleHeader(vfile, intf, doc)
@@ -153,6 +155,12 @@ class _ToVerilogConvertor(object):
             _writeTestBench(tbfile, intf)
             tbfile.close()
 
+        ### clean-up properly ###
+        self._cleanup(siglist)
+        
+        return h.top
+        
+    def _cleanup(self, siglist):
         # clean up signal names
         for sig in siglist:
             sig._clear()
@@ -169,7 +177,11 @@ class _ToVerilogConvertor(object):
         self.no_myhdl_header = False
         self.no_testbench = False
         
-        return h.top
+        
+    def _convert_filter(self, h, intf, siglist, memlist, genlist):
+        # intended to be a entry point for other uses: 
+        #  code checking, optimizations, etc
+        pass
     
 
 toVerilog = _ToVerilogConvertor()