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0.9 dev branch

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--HG--
branch : 0.9-dev
This commit is contained in:
Keerthan Jaic 2013-08-07 17:40:39 -04:00
parent 247d0379e2
commit a99b67432f
1 changed files with 3 additions and 3 deletions
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6
myhdl/__init__.py
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@ -40,7 +40,7 @@ bin -- returns a binary string representation.
concat -- function to concat ints, bitstrings, bools, intbvs, Signals
-- returns an intbv
instances -- function that returns all instances defined in a function
always --
always --
always_comb -- decorator that returns an input-sensitive generator
always_seq --
ResetSignal --
@ -50,7 +50,7 @@ toVerilog -- function that converts a design to Verilog
"""
__version__ = "0.8"
__version__ = "0.9-dev"
import sys
import warnings
@ -168,7 +168,7 @@ __all__ = ["bin",
"toVerilog",
"toVHDL",
"conversion",
"Tristate"
"Tristate"
]