From a99b67432f26b48248a2751a51f0f71625c831f1 Mon Sep 17 00:00:00 2001
From: Keerthan Jaic <jckeerthan@gmail.com>
Date: Wed, 7 Aug 2013 17:40:39 -0400
Subject: [PATCH] 0.9 dev branch

--HG--
branch : 0.9-dev
---
 myhdl/__init__.py | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/myhdl/__init__.py b/myhdl/__init__.py
index 598bb0e1..2189bc23 100644
--- a/myhdl/__init__.py
+++ b/myhdl/__init__.py
@@ -40,7 +40,7 @@ bin -- returns a binary string representation.
 concat -- function to concat ints, bitstrings, bools, intbvs, Signals
        -- returns an intbv
 instances -- function that returns all instances defined in a function
-always -- 
+always --
 always_comb -- decorator that returns an input-sensitive generator
 always_seq --
 ResetSignal --
@@ -50,7 +50,7 @@ toVerilog -- function that converts a design to Verilog
 
 """
 
-__version__ = "0.8"
+__version__ = "0.9-dev"
 
 import sys
 import warnings
@@ -168,7 +168,7 @@ __all__ = ["bin",
            "toVerilog",
            "toVHDL",
            "conversion",
-           "Tristate"           
+           "Tristate"
            ]