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_toVerilog.py: 'skip_zero_mem_init': added *forgotten* condition taht the initail value must be zero to be able to skip the genberation of the initial block (#432)

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Josy Boelen 2024-06-12 10:20:27 +02:00 committed by GitHub
parent 6520f32194
commit ac9b87c273
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2 changed files with 2 additions and 2 deletions
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2
myhdl/__init__.py
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@ -49,7 +49,7 @@ traceSignals -- function that enables signal tracing in a VCD file
toVerilog -- function that converts a design to Verilog
"""
__version__ = "0.11.47"
__version__ = "0.11.48"
class StopSimulation(Exception):

2
myhdl/conversion/_toVerilog.py
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@ -381,7 +381,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
if toVerilog.initial_values and not k == 'wire':
if all([each._init == m.mem[0]._init for each in m.mem]):
if toVerilog.initial_values == 'skip_zero_mem_init':
if toVerilog.initial_values == 'skip_zero_mem_init' and _intRepr(m.mem[0]._init) == 0:
pass
else:
initialize_block_name = ('INITIALIZE_' + m.name).upper()