From ac9b87c2731986193c76d62750c20e37dc3d43ff Mon Sep 17 00:00:00 2001 From: Josy Boelen Date: Wed, 12 Jun 2024 10:20:27 +0200 Subject: [PATCH] _toVerilog.py: 'skip_zero_mem_init': added *forgotten* condition taht the initail value must be zero to be able to skip the genberation of the initial block (#432) --- myhdl/__init__.py | 2 +- myhdl/conversion/_toVerilog.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/myhdl/__init__.py b/myhdl/__init__.py index 31c1c34f..e5f8e15e 100644 --- a/myhdl/__init__.py +++ b/myhdl/__init__.py @@ -49,7 +49,7 @@ traceSignals -- function that enables signal tracing in a VCD file toVerilog -- function that converts a design to Verilog """ -__version__ = "0.11.47" +__version__ = "0.11.48" class StopSimulation(Exception): diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py index 6685460d..10af1f0d 100644 --- a/myhdl/conversion/_toVerilog.py +++ b/myhdl/conversion/_toVerilog.py @@ -381,7 +381,7 @@ def _writeSigDecls(f, intf, siglist, memlist): if toVerilog.initial_values and not k == 'wire': if all([each._init == m.mem[0]._init for each in m.mem]): - if toVerilog.initial_values == 'skip_zero_mem_init': + if toVerilog.initial_values == 'skip_zero_mem_init' and _intRepr(m.mem[0]._init) == 0: pass else: initialize_block_name = ('INITIALIZE_' + m.name).upper()