FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

_toVerilog.py: 'skip_zero_mem_init': added *forgotten* condition taht the initail value must be zero to be able to skip the genberation of the initial block (#432)

Browse Source
This commit is contained in:
Josy Boelen 2024-06-12 10:20:27 +02:00 committed by GitHub
parent 6520f32194
commit ac9b87c273
No known key found for this signature in database
GPG Key ID: B5690EEEBB952194
2 changed files with 2 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
myhdl/__init__.py
View File

@ -49,7 +49,7 @@ traceSignals -- function that enables signal tracing in a VCD file
toVerilog -- function that converts a design to Verilog toVerilog -- function that converts a design to Verilog
""" """
__version__ = "0.11.47" __version__ = "0.11.48"
class StopSimulation(Exception): class StopSimulation(Exception):

2
myhdl/conversion/_toVerilog.py
View File

@ -381,7 +381,7 @@ def _writeSigDecls(f, intf, siglist, memlist):
if toVerilog.initial_values and not k == 'wire': if toVerilog.initial_values and not k == 'wire':
if all([each._init == m.mem[0]._init for each in m.mem]): if all([each._init == m.mem[0]._init for each in m.mem]):
if toVerilog.initial_values == 'skip_zero_mem_init': if toVerilog.initial_values == 'skip_zero_mem_init' and _intRepr(m.mem[0]._init) == 0:
pass pass
else: else:
initialize_block_name = ('INITIALIZE_' + m.name).upper() initialize_block_name = ('INITIALIZE_' + m.name).upper()