FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00
Code Issues Projects Releases Wiki Activity

merge from default

Browse Source 
--HG--
branch : 0.8-dev
This commit is contained in:
Jan Decaluwe 2012-05-30 17:45:02 +02:00
commit ae5e0da1ee
1 changed files with 4 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
myhdl/conversion/_analyze.py
View File

@ -160,8 +160,11 @@ def _analyzeGens(top, absnames):
for n, c in zip(f.func_code.co_freevars, f.func_closure): for n, c in zip(f.func_code.co_freevars, f.func_closure):
obj = _cell_deref(c) obj = _cell_deref(c)
if isinstance(g, _AlwaysComb): if isinstance(g, _AlwaysComb):
if not (isinstance(obj, (int, long, _Signal)) or _isMem(obj) or _isTupleOfInts(obj)): if not ( isinstance(obj, (int, long, EnumType,_Signal)) or \
_isMem(obj) or _isTupleOfInts(obj)
):
info = "File %s, line %s: " % (tree.sourcefile, tree.lineoffset) info = "File %s, line %s: " % (tree.sourcefile, tree.lineoffset)
print type(obj)
raise ConversionError(_error.UnsupportedType, n, info) raise ConversionError(_error.UnsupportedType, n, info)
tree.symdict[n] = obj tree.symdict[n] = obj
tree.name = absnames.get(id(g), str(_Label("BLOCK"))).upper() tree.name = absnames.get(id(g), str(_Label("BLOCK"))).upper()