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clean up

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jand 2003-11-30 00:13:29 +00:00
parent 747f088c47
commit aea5f25812
1 changed files with 0 additions and 19 deletions
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19
myhdl/_toVerilog.py
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@ -350,7 +350,6 @@ class _AnalyzeVisitor(_NotSupportedVisitor, _ToVerilogMixin):
ast.returnObj = v.returnObj ast.returnObj = v.returnObj
ast.kind = v.kind ast.kind = v.kind
node.ast = ast node.ast = ast
print "FUNCTION inputs %s outputs %s" % (ast.inputs, ast.outputs)
for i, arg in enumerate(node.args): for i, arg in enumerate(node.args):
if isinstance(arg, compiler.ast.Keyword): if isinstance(arg, compiler.ast.Keyword):
n = arg.name n = arg.name
@ -565,7 +564,6 @@ class _AnalyzeFuncVisitor(_AnalyzeVisitor):
self.hasReturn = True self.hasReturn = True
def _analyzeTopFunc(func, *args, **kwargs): def _analyzeTopFunc(func, *args, **kwargs):
s = inspect.getsource(func) s = inspect.getsource(func)
s = s.lstrip() s = s.lstrip()
@ -575,14 +573,6 @@ def _analyzeTopFunc(func, *args, **kwargs):
return v return v
#Masks for co_flags
#define CO_OPTIMIZED 0x0001
#define CO_NEWLOCALS 0x0002
#define CO_VARARGS 0x0004
#define CO_VARKEYWORDS 0x0008
#define CO_NESTED 0x0010
#define CO_GENERATOR 0x0020
class _AnalyzeTopFuncVisitor(object): class _AnalyzeTopFuncVisitor(object):
def __init__(self, *args, **kwargs): def __init__(self, *args, **kwargs):
@ -702,10 +692,6 @@ def _convertGens(genlist, vfile):
Visitor = _ConvertInitialVisitor Visitor = _ConvertInitialVisitor
v = Visitor(ast, blockBuf, funcBuf) v = Visitor(ast, blockBuf, funcBuf)
compiler.walk(ast, v) compiler.walk(ast, v)
#print "FUNC"
#print funcBuf.getvalue()
#print "BLOCK"
#print blockBuf.getvalue()
vfile.write(funcBuf.getvalue()); funcBuf.close() vfile.write(funcBuf.getvalue()); funcBuf.close()
vfile.write(blockBuf.getvalue()); blockBuf.close() vfile.write(blockBuf.getvalue()); blockBuf.close()
@ -773,8 +759,6 @@ class _ConvertVisitor(_ToVerilogMixin):
self.multiOp(node, '&&') self.multiOp(node, '&&')
def visitAssAttr(self, node): def visitAssAttr(self, node):
# if not node.a
# assert node.attrname == 'next'
if node.attrname != 'next': if node.attrname != 'next':
self.raiseError(node, _error.NotSupported, "attribute assignment") self.raiseError(node, _error.NotSupported, "attribute assignment")
self.isSigAss = True self.isSigAss = True
@ -1075,8 +1059,6 @@ class _ConvertVisitor(_ToVerilogMixin):
self.binaryOp(node, '>>') self.binaryOp(node, '>>')
def visitSlice(self, node): def visitSlice(self, node):
# print dir(node)
# print node.obj
if isinstance(node.expr, ast.CallFunc) and \ if isinstance(node.expr, ast.CallFunc) and \
node.expr.node.obj is intbv: node.expr.node.obj is intbv:
c = self.getVal(node) c = self.getVal(node)
@ -1306,4 +1288,3 @@ class _ConvertTaskVisitor(_ConvertVisitor):
self.writeline() self.writeline()
self.write("endtask") self.write("endtask")
self.writeline(2) self.writeline(2)