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clean up
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parent
747f088c47
commit
aea5f25812
@ -350,7 +350,6 @@ class _AnalyzeVisitor(_NotSupportedVisitor, _ToVerilogMixin):
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ast.returnObj = v.returnObj
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ast.kind = v.kind
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node.ast = ast
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print "FUNCTION inputs %s outputs %s" % (ast.inputs, ast.outputs)
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for i, arg in enumerate(node.args):
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if isinstance(arg, compiler.ast.Keyword):
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n = arg.name
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@ -565,7 +564,6 @@ class _AnalyzeFuncVisitor(_AnalyzeVisitor):
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self.hasReturn = True
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def _analyzeTopFunc(func, *args, **kwargs):
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s = inspect.getsource(func)
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s = s.lstrip()
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@ -575,14 +573,6 @@ def _analyzeTopFunc(func, *args, **kwargs):
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return v
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#Masks for co_flags
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#define CO_OPTIMIZED 0x0001
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#define CO_NEWLOCALS 0x0002
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#define CO_VARARGS 0x0004
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#define CO_VARKEYWORDS 0x0008
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#define CO_NESTED 0x0010
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#define CO_GENERATOR 0x0020
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class _AnalyzeTopFuncVisitor(object):
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def __init__(self, *args, **kwargs):
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@ -702,10 +692,6 @@ def _convertGens(genlist, vfile):
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Visitor = _ConvertInitialVisitor
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v = Visitor(ast, blockBuf, funcBuf)
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compiler.walk(ast, v)
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#print "FUNC"
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#print funcBuf.getvalue()
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#print "BLOCK"
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#print blockBuf.getvalue()
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vfile.write(funcBuf.getvalue()); funcBuf.close()
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vfile.write(blockBuf.getvalue()); blockBuf.close()
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@ -773,8 +759,6 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.multiOp(node, '&&')
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def visitAssAttr(self, node):
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# if not node.a
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# assert node.attrname == 'next'
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if node.attrname != 'next':
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self.raiseError(node, _error.NotSupported, "attribute assignment")
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self.isSigAss = True
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@ -1075,8 +1059,6 @@ class _ConvertVisitor(_ToVerilogMixin):
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self.binaryOp(node, '>>')
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def visitSlice(self, node):
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# print dir(node)
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# print node.obj
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if isinstance(node.expr, ast.CallFunc) and \
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node.expr.node.obj is intbv:
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c = self.getVal(node)
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@ -1306,4 +1288,3 @@ class _ConvertTaskVisitor(_ConvertVisitor):
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self.writeline()
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self.write("endtask")
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self.writeline(2)
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