From b13553eefba85f7673d3d5f8a4608a8c1f9e3478 Mon Sep 17 00:00:00 2001 From: Jan Decaluwe Date: Sat, 12 Mar 2016 09:20:20 +0100 Subject: [PATCH] Rename module -> block --- example/cookbook/bitonic/bitonic.py | 10 +- example/manual/fsm.py | 4 +- example/manual/fsm3.py | 2 +- myhdl/_Simulation.py | 6 +- myhdl/__init__.py | 8 +- myhdl/_getHierarchy.py | 4 +- myhdl/_instance.py | 10 +- myhdl/_module.py | 201 ------------------ myhdl/_traceSignals.py | 18 +- myhdl/conversion/_toVHDL.py | 12 +- myhdl/conversion/_toVerilog.py | 16 +- myhdl/conversion/_verify.py | 10 +- .../conversion/general/test_ShadowSignal.py | 12 +- myhdl/test/conversion/general/test_adapter.py | 4 +- .../test/conversion/general/test_bin2gray.py | 9 +- myhdl/test/conversion/general/test_case.py | 11 +- .../test/conversion/general/test_constants.py | 2 +- myhdl/test/conversion/general/test_dec.py | 12 +- myhdl/test/conversion/general/test_errors.py | 15 +- myhdl/test/conversion/general/test_fsm.py | 4 +- myhdl/test/conversion/general/test_hec.py | 4 +- myhdl/test/conversion/general/test_inc.py | 14 +- .../conversion/general/test_intbv_signed.py | 6 +- .../conversion/general/test_interfaces1.py | 8 +- .../conversion/general/test_interfaces2.py | 8 +- .../conversion/general/test_interfaces3.py | 18 +- .../conversion/general/test_interfaces4.py | 8 +- .../conversion/general/test_listofsigs.py | 32 +-- myhdl/test/conversion/general/test_loops.py | 40 ++-- myhdl/test/conversion/general/test_method.py | 14 +- myhdl/test/conversion/general/test_numass.py | 2 +- myhdl/test/conversion/general/test_ram.py | 12 +- .../conversion/general/test_randscrambler.py | 8 +- myhdl/test/conversion/general/test_rom.py | 10 +- myhdl/test/conversion/general/test_set_dir.py | 2 +- myhdl/test/conversion/general/test_ternary.py | 6 +- .../general/test_toplevel_method.py | 25 +-- myhdl/test/conversion/toVHDL/test_custom.py | 24 +-- .../toVerilog/test_RandomScrambler.py | 6 +- .../test/conversion/toVerilog/test_custom.py | 16 +- myhdl/test/core/test_traceSignals.py | 21 +- 41 files changed, 221 insertions(+), 433 deletions(-) delete mode 100644 myhdl/_module.py diff --git a/example/cookbook/bitonic/bitonic.py b/example/cookbook/bitonic/bitonic.py index ad5cb37d..fb83f363 100644 --- a/example/cookbook/bitonic/bitonic.py +++ b/example/cookbook/bitonic/bitonic.py @@ -6,7 +6,7 @@ from myhdl.conversion import analyze DESCENDING, ASCENDING = False, True -@myhdl.module +@block def comp(a1, a2, z1, z2, dir): @always_comb @@ -20,7 +20,7 @@ def comp(a1, a2, z1, z2, dir): return logic -@myhdl.module +@block def feedthru(a, z): @always_comb @@ -30,7 +30,7 @@ def feedthru(a, z): return logic -@myhdl.module +@block def bitonicMerge(a, z, dir): n = len(a) @@ -49,7 +49,7 @@ def bitonicMerge(a, z, dir): return feedthru(a[0], z[0]) -@myhdl.module +@block def bitonicSort(a, z, dir): n = len(a) @@ -68,7 +68,7 @@ def bitonicSort(a, z, dir): else: return feedthru(a[0], z[0]) -@myhdl.module +@block def Array8Sorter(a0, a1, a2, a3, a4, a5, a6, a7, z0, z1, z2, z3, z4, z5, z6, z7): diff --git a/example/manual/fsm.py b/example/manual/fsm.py index a133da1a..ff527d8a 100644 --- a/example/manual/fsm.py +++ b/example/manual/fsm.py @@ -5,7 +5,7 @@ ACTIVE_LOW = 0 FRAME_SIZE = 8 t_State = enum('SEARCH', 'CONFIRM', 'SYNC') -@myhdl.module +@block def FramerCtrl(SOF, state, syncFlag, clk, reset_n): """ Framing control FSM. @@ -55,7 +55,7 @@ def FramerCtrl(SOF, state, syncFlag, clk, reset_n): return FSM -@myhdl.module +@block def testbench(): SOF = Signal(bool(0)) diff --git a/example/manual/fsm3.py b/example/manual/fsm3.py index 4205d570..0e3a5571 100644 --- a/example/manual/fsm3.py +++ b/example/manual/fsm3.py @@ -10,7 +10,7 @@ ACTIVE_LOW = bool(0) FRAME_SIZE = 8 t_State = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot") -@myhdl.module +@block def FramerCtrl(SOF, state, syncFlag, clk, reset_n): """ Framing control FSM. diff --git a/myhdl/_Simulation.py b/myhdl/_Simulation.py index 3abc210e..a83326b1 100644 --- a/myhdl/_Simulation.py +++ b/myhdl/_Simulation.py @@ -34,7 +34,7 @@ from myhdl._simulator import _signals, _siglist, _futureEvents from myhdl._Waiter import _Waiter, _inferWaiter, _SignalWaiter,_SignalTupleWaiter from myhdl._util import _printExcInfo from myhdl._instance import _Instantiator -from myhdl._module import _ModuleInstance +from myhdl._block import _BlockInstance from myhdl._ShadowSignal import _ShadowSignal schedule = _futureEvents.append @@ -45,11 +45,11 @@ _error.ArgType = "Inappriopriate argument type" _error.MultipleCosim = "Only a single cosimulator argument allowed" _error.DuplicatedArg = "Duplicated argument" -# flatten Module objects out +# flatten Block objects out def _flatten(*args): arglist = [] for arg in args: - if isinstance(arg, _ModuleInstance): + if isinstance(arg, _BlockInstance): arg = arg.subs if isinstance(arg, (list, tuple, set)): for item in arg: diff --git a/myhdl/__init__.py b/myhdl/__init__.py index 32620d49..8ee7ee72 100644 --- a/myhdl/__init__.py +++ b/myhdl/__init__.py @@ -82,9 +82,9 @@ class AlwaysCombError(Error): pass class InstanceError(Error): pass -class ModuleError(Error): +class BlockError(Error): pass -class ModuleInstanceError(Error): +class BlockInstanceError(Error): pass class CosimulationError(Error): pass @@ -134,7 +134,7 @@ from ._always_comb import always_comb from ._always_seq import always_seq, ResetSignal from ._always import always from ._instance import instance -from ._module import module +from ._block import block from ._enum import enum, EnumType, EnumItemType from ._traceSignals import traceSignals @@ -164,7 +164,7 @@ __all__ = ["bin", "Simulation", "instances", "instance", - "module", + "block", "always_comb", "always_seq", "ResetSignal", diff --git a/myhdl/_getHierarchy.py b/myhdl/_getHierarchy.py index 8a4559c3..ca4dbd01 100644 --- a/myhdl/_getHierarchy.py +++ b/myhdl/_getHierarchy.py @@ -25,7 +25,7 @@ from __future__ import absolute_import from myhdl._extractHierarchy import _Instance from myhdl._instance import _Instantiator -from myhdl._module import _ModuleInstance +from myhdl._block import _BlockInstance class _Hierarchy(object): def __init__(self, name, modinst): @@ -59,5 +59,5 @@ def _getHierarchyHelper(level, modinst, hierarchy): inst = _Instance(level, modinst, subs, modinst.sigdict, modinst.memdict) hierarchy.append(inst) for inst in modinst.subs: - if isinstance(inst, _ModuleInstance): + if isinstance(inst, _BlockInstance): _getHierarchyHelper(level+1, inst, hierarchy) diff --git a/myhdl/_instance.py b/myhdl/_instance.py index 0af8db7d..9fff0f79 100644 --- a/myhdl/_instance.py +++ b/myhdl/_instance.py @@ -45,15 +45,15 @@ class _CallInfo(object): def _getCallInfo(): """Get info on the caller of an Instantiator. - An Instantiator should be used in a module context. + An Instantiator should be used in a block context. This function gets the required info about the caller. It uses the frame stack: 0: this function 1: the instantiator decorator - 2: the module function that defines instances - 3: the caller of the module function, e.g. the ModuleInstance. + 2: the block function that defines instances + 3: the caller of the block function, e.g. the BlockInstance. """ - from myhdl import _module + from myhdl import _block funcrec = inspect.stack()[2] name = funcrec[3] frame = funcrec[0] @@ -63,7 +63,7 @@ def _getCallInfo(): callerrec = inspect.stack()[3] f_locals = callerrec[0].f_locals if 'self' in f_locals: - modctxt = isinstance(f_locals['self'], _module._ModuleInstance) + modctxt = isinstance(f_locals['self'], _block._BlockInstance) return _CallInfo(name, modctxt, symdict) diff --git a/myhdl/_module.py b/myhdl/_module.py deleted file mode 100644 index b0a98086..00000000 --- a/myhdl/_module.py +++ /dev/null @@ -1,201 +0,0 @@ -# This file is part of the myhdl library, a Python package for using -# Python as a Hardware Description Language. -# -# Copyright (C) 2003-2016 Jan Decaluwe -# -# The myhdl library is free software; you can redistribute it and/or -# modify it under the terms of the GNU Lesser General Public License as -# published by the Free Software Foundation; either version 2.1 of the -# License, or (at your option) any later version. -# -# This library is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -# Lesser General Public License for more details. - -# You should have received a copy of the GNU Lesser General Public -# License along with this library; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA - -""" Module with the @myhdl.module decorator function. """ -from __future__ import absolute_import - -import inspect - -import myhdl -from myhdl import ModuleError -from myhdl._instance import _Instantiator -from myhdl._util import _flatten -from myhdl._extractHierarchy import (_MemInfo, _makeMemInfo, - _UserVerilogCode, _UserVhdlCode) -from myhdl._Signal import _Signal, _isListOfSigs - - -class _error: - pass -_error.ArgType = "A module should return module or instantiator objects" -_error.InstanceError = "%s: submodule %s should be encapsulated in a module decorator" - -class _CallInfo(object): - def __init__(self, name, modctxt, symdict): - self.name = name - self.modctxt = modctxt - self.symdict = symdict - -def _getCallInfo(): - """Get info on the caller of a ModuleInstance. - - A ModuleInstance should be used in a module context. - This function gets the required info from the caller - It uses the frame stack: - 0: this function - 1: module instance constructor - 2: the _Module class __call__() - 3: the function that defines instances - 4: the caller of the module function, e.g. a ModuleInstance. - - There is a complication when the decorator is used on a method. - In this case, it is used as a descriptor, and there is an additional - stack level due to the __get__ method. The current hack is to check - whether we are still in this module at level 3, and increment - all the subsequent levels. - """ - - stack = inspect.stack() - # caller may be undefined if instantiation from a Python module - callerrec = None - # check whether the decorator is used as a descriptor - if (inspect.getmodule(stack[3][0]) is myhdl._module): - funcrec = stack[4] - if len(stack) > 5: - callerrec = stack[5] - else: - funcrec = stack[3] - if len(stack) > 4: - callerrec = stack[4] - name = funcrec[3] - frame = funcrec[0] - symdict = dict(frame.f_globals) - symdict.update(frame.f_locals) - modctxt = False - if callerrec is not None: - f_locals = callerrec[0].f_locals - if 'self' in f_locals: - modctxt = isinstance(f_locals['self'], _ModuleInstance) - return _CallInfo(name, modctxt, symdict) - - -def module(modfunc): - return _Module(modfunc) - -class _Module(object): - - def __init__(self, modfunc): - self.modfunc = modfunc - self.__name__ = self.name = modfunc.__name__ - self.sourcefile = inspect.getsourcefile(modfunc) - self.sourceline = inspect.getsourcelines(modfunc)[0] - self.count = 0 - - def __call__(self, *args, **kwargs): - modinst = _ModuleInstance(self, *args, **kwargs) - self.count += 1 - return modinst - - # This is the way to make the module decorator work on methods - # Turn it into a descriptor, used when accessed as an attribute - # In that case, the object is bound to the call method - # like done automatically for classic bound methods - # http://stackoverflow.com/a/3296318/574895 - # Avoid functools to have identical behavior between - # CPython and PyPy - def __get__(self, obj, objtype): - """Support instance methods.""" - def f(*args, **kwargs): - return self.__call__(obj, *args, **kwargs) - return f - - -class _ModuleInstance(object): - - def __init__(self, mod, *args, **kwargs): - self.args = args - self.kwargs = kwargs - self.mod = mod - self.__doc__ = mod.modfunc.__doc__ - callinfo = _getCallInfo() - self.callinfo = callinfo - self.modctxt = callinfo.modctxt - self.callername = callinfo.name - self.symdict = None - self.sigdict = {} - self.memdict = {} - # flatten, but keep ModuleInstance objects - self.subs = _flatten(mod.modfunc(*args, **kwargs)) - self._verifySubs() - self._updateNamespaces() - self.name = self.__name__ = mod.__name__ + '_' + str(mod.count) - self.verilog_code = self.vhdl_code = None - if hasattr(mod, 'verilog_code'): - self.verilog_code = _UserVerilogCode(mod.verilog_code, self.symdict, mod.name, - mod.modfunc, mod.sourcefile, mod.sourceline) - if hasattr(mod, 'vhdl_code'): - self.vhdl_code = _UserVhdlCode(mod.vhdl_code, self.symdict, mod.name, - mod.modfunc, mod.sourcefile, mod.sourceline) - - def _verifySubs(self): - for inst in self.subs: - # print (inst.name, type(inst)) - if not isinstance(inst, (_ModuleInstance, _Instantiator)): - raise ModuleError(_error.ArgType) - if not inst.modctxt: - raise ModuleError(_error.InstanceError % (self.mod.name, inst.callername)) - - def _updateNamespaces(self): - # dicts to keep track of objects used in Instantiator objects - usedsigdict = {} - usedlosdict = {} - for inst in self.subs: - # the symdict of a module instance is defined by - # the call context of its instantiations - if self.symdict is None: - self.symdict = inst.callinfo.symdict - if isinstance(inst, _Instantiator): - usedsigdict.update(inst.sigdict) - usedlosdict.update(inst.losdict) - if self.symdict is None: - self.symdict = {} - # Special case: due to attribute reference transformation, the - # sigdict and losdict from Instantiator objects may contain new - # references. Therefore, update the symdict with them. - # To be revisited. - self.symdict.update(usedsigdict) - self.symdict.update(usedlosdict) - # Infer sigdict and memdict, with compatibility patches from _extractHierarchy - for n, v in self.symdict.items(): - if isinstance(v, _Signal): - self.sigdict[n] = v - if n in usedsigdict: - v._markUsed() - if _isListOfSigs(v): - m = _makeMemInfo(v) - self.memdict[n] = m - if n in usedlosdict: - m._used = True - - def _inferInterface(self): - from myhdl.conversion._analyze import _analyzeTopFunc - intf = _analyzeTopFunc(self.mod.modfunc, *self.args, **self.kwargs) - self.argnames = intf.argnames - self.argdict = intf.argdict - - def verify(self): - return myhdl.conversion.verify(self) - - def convert(self, hdl='Verilog'): - if hdl == 'VHDL': - return myhdl.conversion._toVHDL.toVHDL(self) - elif hdl == 'Verilog': - return myhdl.conversion._toVerilog.toVerilog(self) - else: - raise ModuleInstanceError('unknown hdl %s' % hdl) diff --git a/myhdl/_traceSignals.py b/myhdl/_traceSignals.py index b7129cca..b7a48421 100644 --- a/myhdl/_traceSignals.py +++ b/myhdl/_traceSignals.py @@ -17,7 +17,7 @@ # License along with this library; if not, write to the Free Software # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA -""" myhdl traceSignals module. +""" myhdl traceSignals block. """ from __future__ import absolute_import @@ -36,7 +36,7 @@ from myhdl import _simulator, __version__, EnumItemType from myhdl._extractHierarchy import _HierExtr from myhdl import TraceSignalsError from myhdl._ShadowSignal import _TristateSignal, _TristateDriver -from myhdl._module import _Module, _ModuleInstance +from myhdl._block import _Block, _BlockInstance from myhdl._getHierarchy import _getHierarchy _tracing = 0 @@ -68,9 +68,9 @@ class _TraceSignalsClass(object): def __call__(self, dut, *args, **kwargs): global _tracing, vcdpath - if isinstance(dut, _ModuleInstance): + if isinstance(dut, _BlockInstance): # now we go bottom-up: so clean up and start over - # TODO: consider a warning for the overruled module + # TODO: consider a warning for the overruled block if _simulator._tracing: _simulator._tracing = 0 _simulator._tf.close() @@ -85,7 +85,7 @@ class _TraceSignalsClass(object): from myhdl.conversion import _toVerilog if _toVerilog._converting: raise TraceSignalsError("Cannot use traceSignals while converting to Verilog") - if not isinstance(dut, _ModuleInstance): + if not isinstance(dut, _BlockInstance): if not callable(dut): raise TraceSignalsError(_error.ArgType, "got %s" % type(dut)) if _simulator._tracing: @@ -95,7 +95,7 @@ class _TraceSignalsClass(object): try: if self.name is None: name = dut.__name__ - if isinstance(dut, _ModuleInstance): + if isinstance(dut, _BlockInstance): name = dut.mod.__name__ else: name = str(self.name) @@ -107,10 +107,10 @@ class _TraceSignalsClass(object): else: directory = self.directory - if isinstance(dut, _Module): - raise TypeError("Module %s: conversion should be on an instance" % dut.__name__) + if isinstance(dut, _Block): + raise TypeError("Block %s: conversion should be on an instance" % dut.__name__) - if isinstance(dut, _ModuleInstance): + if isinstance(dut, _BlockInstance): h = _getHierarchy(name, dut) else: warnings.warn("\n traceSignals(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html", stacklevel=2) diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py index d5c5d455..d5483fa5 100644 --- a/myhdl/conversion/_toVHDL.py +++ b/myhdl/conversion/_toVHDL.py @@ -56,7 +56,7 @@ from myhdl._util import _flatten from myhdl._compat import integer_types, class_types, StringIO from myhdl._ShadowSignal import _TristateSignal, _TristateDriver -from myhdl._module import _ModuleInstance +from myhdl._block import _BlockInstance from myhdl._getHierarchy import _getHierarchy _version = myhdl.__version__.replace('.','') @@ -73,7 +73,7 @@ def _checkArgs(arglist): def _flatten(*args): arglist = [] for arg in args: - if isinstance(arg, _ModuleInstance): + if isinstance(arg, _BlockInstance): if arg.vhdl_code is not None: arglist.append(arg.vhdl_code) continue @@ -134,19 +134,19 @@ class _ToVHDLConvertor(object): from myhdl import _traceSignals if _traceSignals._tracing: raise ToVHDLError("Cannot use toVHDL while tracing signals") - if not isinstance(func, _ModuleInstance): + if not isinstance(func, _BlockInstance): if not callable(func): raise ToVHDLError(_error.FirstArgType, "got %s" % type(func)) _converting = 1 if self.name is None: name = func.__name__ - if isinstance(func, _ModuleInstance): + if isinstance(func, _BlockInstance): name = func.mod.__name__ else: name = str(self.name) - if isinstance(func, _ModuleInstance): + if isinstance(func, _BlockInstance): try: h = _getHierarchy(name, func) finally: @@ -190,7 +190,7 @@ class _ToVHDLConvertor(object): _annotateTypes(genlist) ### infer interface - if isinstance(func, _ModuleInstance): + if isinstance(func, _BlockInstance): # infer interface after signals have been analyzed func._inferInterface() intf = func diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py index f1ea4849..102e5c64 100644 --- a/myhdl/conversion/_toVerilog.py +++ b/myhdl/conversion/_toVerilog.py @@ -53,7 +53,7 @@ from myhdl.conversion._analyze import (_analyzeSigs, _analyzeGens, _analyzeTopFu from myhdl._Signal import _Signal from myhdl._ShadowSignal import _TristateSignal, _TristateDriver -from myhdl._module import _Module, _ModuleInstance +from myhdl._block import _Block, _BlockInstance from myhdl._getHierarchy import _getHierarchy _converting = 0 @@ -67,7 +67,7 @@ def _checkArgs(arglist): def _flatten(*args): arglist = [] for arg in args: - if isinstance(arg, _ModuleInstance): + if isinstance(arg, _BlockInstance): if arg.verilog_code is not None: arglist.append(arg.verilog_code) continue @@ -130,27 +130,27 @@ class _ToVerilogConvertor(object): from myhdl import _traceSignals if _traceSignals._tracing: raise ToVerilogError("Cannot use toVerilog while tracing signals") - if not isinstance(func, _ModuleInstance): + if not isinstance(func, _BlockInstance): if not callable(func): raise ToVerilogError(_error.FirstArgType, "got %s" % type(func)) _converting = 1 if self.name is None: name = func.__name__ - if isinstance(func, _ModuleInstance): + if isinstance(func, _BlockInstance): name = func.mod.__name__ else: name = str(self.name) - if isinstance(func, _ModuleInstance): + if isinstance(func, _BlockInstance): try: h = _getHierarchy(name, func) finally: _converting = 0 else: warnings.warn("\n toVerilog(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html", stacklevel=2) - if isinstance(func, _Module): - raise TypeError("Module %s: conversion should be on an instance" % func.__name__) + if isinstance(func, _Block): + raise TypeError("Block %s: conversion should be on an instance" % func.__name__) try: h = _HierExtr(name, func, *args, **kwargs) finally: @@ -176,7 +176,7 @@ class _ToVerilogConvertor(object): _annotateTypes(genlist) ### infer interface - if isinstance(func, _ModuleInstance): + if isinstance(func, _BlockInstance): # infer interface after signals have been analyzed func._inferInterface() intf = func diff --git a/myhdl/conversion/_verify.py b/myhdl/conversion/_verify.py index 7370f9ae..d483a2d2 100644 --- a/myhdl/conversion/_verify.py +++ b/myhdl/conversion/_verify.py @@ -13,7 +13,7 @@ import myhdl from myhdl._Simulation import Simulation from myhdl.conversion._toVHDL import toVHDL from myhdl.conversion._toVerilog import toVerilog -from myhdl._module import _Module, _ModuleInstance +from myhdl._block import _Block, _BlockInstance _version = myhdl.__version__.replace('.','') # strip 'dev' for version @@ -114,7 +114,7 @@ class _VerificationClass(object): name = toVerilog.name elif hdl == 'VHDL' and toVHDL.name is not None: name = toVHDL.name - elif isinstance(func, _ModuleInstance): + elif isinstance(func, _BlockInstance): name = func.mod.__name__ else: warnings.warn("\n analyze()/verify(): Deprecated usage: See http://dev.myhdl.org/meps/mep-114.html", stacklevel=2) @@ -137,14 +137,14 @@ class _VerificationClass(object): skipchars = hdlsim.skipchars ignore = hdlsim.ignore - if isinstance(func, _ModuleInstance): + if isinstance(func, _BlockInstance): if hdl == "VHDL": inst = func.convert(hdl='VHDL') else: inst = func.convert(hdl='Verilog') else: - if isinstance(func, _Module): - raise TypeError("Module %s: conversion should be on an instance" % func.__name__) + if isinstance(func, _Block): + raise TypeError("Block %s: conversion should be on an instance" % func.__name__) if hdl == "VHDL": inst = toVHDL(func, *args, **kwargs) else: diff --git a/myhdl/test/conversion/general/test_ShadowSignal.py b/myhdl/test/conversion/general/test_ShadowSignal.py index 2f9eac9a..22d663d1 100644 --- a/myhdl/test/conversion/general/test_ShadowSignal.py +++ b/myhdl/test/conversion/general/test_ShadowSignal.py @@ -2,7 +2,7 @@ from __future__ import absolute_import import myhdl from myhdl import * -@myhdl.module +@block def bench_SliceSignal(): s = Signal(intbv(0)[8:]) @@ -30,7 +30,7 @@ def test_SliceSignal(): assert conversion.verify(bench_SliceSignal()) == 0 -@myhdl.module +@block def bench_ConcatSignal(): a = Signal(intbv(0)[5:]) @@ -62,7 +62,7 @@ def bench_ConcatSignal(): def test_ConcatSignal(): assert conversion.verify(bench_ConcatSignal()) == 0 -@myhdl.module +@block def bench_ConcatSignalWithConsts(): a = Signal(intbv(0)[5:]) @@ -105,7 +105,7 @@ def test_ConcatSignalWithConsts(): assert conversion.verify(bench_ConcatSignalWithConsts()) == 0 -@myhdl.module +@block def bench_TristateSignal(): s = TristateSignal(intbv(0)[8:]) a = s.driver() @@ -141,7 +141,7 @@ def test_TristateSignal(): assert conversion.verify(bench_TristateSignal()) == 0 -@myhdl.module +@block def permute(x, a, mapping): p = [a(m) for m in mapping] @@ -155,7 +155,7 @@ def permute(x, a, mapping): return assign -@myhdl.module +@block def bench_permute(conv=False): x = Signal(intbv(0)[3:]) diff --git a/myhdl/test/conversion/general/test_adapter.py b/myhdl/test/conversion/general/test_adapter.py index ed9a2df4..706a71e9 100644 --- a/myhdl/test/conversion/general/test_adapter.py +++ b/myhdl/test/conversion/general/test_adapter.py @@ -2,7 +2,7 @@ from __future__ import absolute_import import myhdl from myhdl import * -@myhdl.module +@block def adapter(o_err, i_err, o_spec, i_spec): nomatch = Signal(bool(0)) @@ -36,7 +36,7 @@ def adapter(o_err, i_err, o_spec, i_spec): return assign -@myhdl.module +@block def bench_adapter(conv=False): o_spec = ('c', 'a', 'other', 'nomatch') i_spec = { 'a' : 1, 'b' : 2, 'c' : 0, 'd' : 3, 'e' : 4, 'f' : 5, } diff --git a/myhdl/test/conversion/general/test_bin2gray.py b/myhdl/test/conversion/general/test_bin2gray.py index 7f3493c0..acdd087b 100644 --- a/myhdl/test/conversion/general/test_bin2gray.py +++ b/myhdl/test/conversion/general/test_bin2gray.py @@ -2,10 +2,9 @@ from __future__ import absolute_import import os path = os.path -import myhdl -from myhdl import Signal, intbv, delay, instance, always_comb +from myhdl import block, Signal, intbv, delay, instance, always_comb -@myhdl.module +@block def bin2gray2(B, G, width): """ Gray encoder. @@ -23,7 +22,7 @@ def bin2gray2(B, G, width): G.next[i] = Bext[i+1] ^ Bext[i] return logic -@myhdl.module +@block def bin2gray(B, G, width): """ Gray encoder. @@ -44,7 +43,7 @@ def bin2gray(B, G, width): return logic -@myhdl.module +@block def bin2grayBench(width, bin2gray): B = Signal(intbv(0)[width:]) diff --git a/myhdl/test/conversion/general/test_case.py b/myhdl/test/conversion/general/test_case.py index 8536ab9d..b813237d 100644 --- a/myhdl/test/conversion/general/test_case.py +++ b/myhdl/test/conversion/general/test_case.py @@ -2,7 +2,7 @@ from __future__ import absolute_import import myhdl from myhdl import * -@myhdl.module +@block def map_case4(z, a): @always_comb @@ -18,7 +18,7 @@ def map_case4(z, a): return logic -@myhdl.module +@block def map_case2(z, a): @always_comb @@ -31,7 +31,7 @@ def map_case2(z, a): return logic -@myhdl.module +@block def map_case3(z, a): @always_comb @@ -45,7 +45,7 @@ def map_case3(z, a): return logic -@myhdl.module +@block def map_case4_full(z, a): @always_comb @@ -62,7 +62,7 @@ def map_case4_full(z, a): return logic -@myhdl.module +@block def bench_case(map_case, N): a = Signal(intbv(0)[2:]) @@ -91,4 +91,3 @@ def test_case3(): def test_case4_full(): assert conversion.verify(bench_case( map_case4_full, 4)) == 0 - diff --git a/myhdl/test/conversion/general/test_constants.py b/myhdl/test/conversion/general/test_constants.py index 79877c10..38264670 100644 --- a/myhdl/test/conversion/general/test_constants.py +++ b/myhdl/test/conversion/general/test_constants.py @@ -2,7 +2,7 @@ from __future__ import absolute_import import myhdl from myhdl import * -@myhdl.module +@block def constants(v, u, x, y, z, a): b = Signal(bool(0)) diff --git a/myhdl/test/conversion/general/test_dec.py b/myhdl/test/conversion/general/test_dec.py index 18a2e483..ec54457d 100644 --- a/myhdl/test/conversion/general/test_dec.py +++ b/myhdl/test/conversion/general/test_dec.py @@ -12,7 +12,7 @@ from myhdl.conversion import verify ACTIVE_LOW, INACTIVE_HIGH = 0, 1 -@myhdl.module +@block def decRef(count, enable, clock, reset, n): """ Decrementer with enable. @@ -37,7 +37,7 @@ def decRef(count, enable, clock, reset, n): return logic -@myhdl.module +@block def dec(count, enable, clock, reset, n): """ Decrementer with enable. @@ -62,7 +62,7 @@ def dec(count, enable, clock, reset, n): return decProcess -@myhdl.module +@block def decFunc(count, enable, clock, reset, n): def decFuncFunc(cnt): @@ -84,7 +84,7 @@ def decFunc(count, enable, clock, reset, n): return decFuncGen -@myhdl.module +@block def decTask(count, enable, clock, reset, n): def decTaskFunc(cnt, enable, reset, n): @@ -110,7 +110,7 @@ def decTask(count, enable, clock, reset, n): return decTaskGen -@myhdl.module +@block def decTaskFreeVar(count, enable, clock, reset, n): def decTaskFunc(): @@ -133,7 +133,7 @@ def decTaskFreeVar(count, enable, clock, reset, n): return decTaskGen -@myhdl.module +@block def DecBench(dec): m = 8 diff --git a/myhdl/test/conversion/general/test_errors.py b/myhdl/test/conversion/general/test_errors.py index 105b1ad7..464f0cb2 100644 --- a/myhdl/test/conversion/general/test_errors.py +++ b/myhdl/test/conversion/general/test_errors.py @@ -6,7 +6,7 @@ from myhdl.conversion._misc import _error from myhdl.conversion import verify -@myhdl.module +@block def sigAugmAssignUnsupported(z, a): @always(a) def logic(): @@ -22,8 +22,8 @@ def test_SigAugmAssignUnsupported(): assert e.kind == _error.NotSupported else: assert False - -@myhdl.module + +@block def modbvRange(z, a, b): @always(a, b) def logic(): @@ -42,8 +42,8 @@ def test_modbvRange(): assert e.kind == _error.ModbvRange else: assert False - -@myhdl.module + +@block def modbvSigRange(z, a, b): @always(a, b) def logic(): @@ -60,8 +60,3 @@ def test_modbvSigRange(): assert e.kind == _error.ModbvRange else: assert False - - - - - diff --git a/myhdl/test/conversion/general/test_fsm.py b/myhdl/test/conversion/general/test_fsm.py index 4763fead..f859abf2 100644 --- a/myhdl/test/conversion/general/test_fsm.py +++ b/myhdl/test/conversion/general/test_fsm.py @@ -13,7 +13,7 @@ t_State_b = enum('SEARCH', 'CONFIRM', 'SYNC') t_State_oh = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot") t_State_oc = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_cold") -@myhdl.module +@block def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State): """ Framing control FSM. @@ -57,7 +57,7 @@ def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State): return FSM -@myhdl.module +@block def FSMBench(FramerCtrl, t_State): SOF = Signal(bool(0)) diff --git a/myhdl/test/conversion/general/test_hec.py b/myhdl/test/conversion/general/test_hec.py index 40481c88..18e41545 100644 --- a/myhdl/test/conversion/general/test_hec.py +++ b/myhdl/test/conversion/general/test_hec.py @@ -58,7 +58,7 @@ def calculateHecTask(hec, header): h ^= COSET hec[:] = h -@myhdl.module +@block def HecCalculatorPlain(hec, header): """ Hec calculation module. @@ -126,7 +126,7 @@ headers = [ 0x00000000, headers.extend([randrange(2**32-1) for i in range(10)]) headers = tuple(headers) -@myhdl.module +@block def HecBench(HecCalculator): hec = Signal(intbv(0)[8:]) diff --git a/myhdl/test/conversion/general/test_inc.py b/myhdl/test/conversion/general/test_inc.py index 3f12c1f5..4a788452 100644 --- a/myhdl/test/conversion/general/test_inc.py +++ b/myhdl/test/conversion/general/test_inc.py @@ -13,7 +13,7 @@ from myhdl.conversion import verify ACTIVE_LOW, INACTIVE_HIGH = bool(0), bool(1) -@myhdl.module +@block def incRef(count, enable, clock, reset, n): """ Incrementer with enable. @@ -34,7 +34,7 @@ def incRef(count, enable, clock, reset, n): count.next = (count + 1) % n return logic -@myhdl.module +@block def inc(count, enable, clock, reset, n): """ Incrementer with enable. @@ -57,7 +57,7 @@ def inc(count, enable, clock, reset, n): return incProcess -@myhdl.module +@block def inc2(count, enable, clock, reset, n): @always(clock.posedge, reset.negedge) @@ -73,7 +73,7 @@ def inc2(count, enable, clock, reset, n): return incProcess -@myhdl.module +@block def incFunc(count, enable, clock, reset, n): def incFuncFunc(cnt, enable): count_next = intbv(0, min=0, max=n) @@ -92,7 +92,7 @@ def incFunc(count, enable, clock, reset, n): return incFuncGen -@myhdl.module +@block def incTask(count, enable, clock, reset, n): def incTaskFunc(cnt, enable, reset, n): @@ -115,7 +115,7 @@ def incTask(count, enable, clock, reset, n): return incTaskGen -@myhdl.module +@block def incTaskFreeVar(count, enable, clock, reset, n): def incTaskFunc(): @@ -133,7 +133,7 @@ def incTaskFreeVar(count, enable, clock, reset, n): return incTaskGen -@myhdl.module +@block def IncBench(inc): NR_CYCLES = 201 diff --git a/myhdl/test/conversion/general/test_intbv_signed.py b/myhdl/test/conversion/general/test_intbv_signed.py index 47300528..1a78d588 100644 --- a/myhdl/test/conversion/general/test_intbv_signed.py +++ b/myhdl/test/conversion/general/test_intbv_signed.py @@ -24,7 +24,7 @@ from __future__ import absolute_import import myhdl from myhdl import * -@myhdl.module +@block def PlainIntbv(): '''Test a plain intbv instance with .signed() @@ -198,7 +198,7 @@ def PlainIntbv(): -@myhdl.module +@block def SlicedSigned(): '''Test a slice with .signed() @@ -225,7 +225,7 @@ def SlicedSigned(): return logic -@myhdl.module +@block def SignedConcat(): '''Test the .signed() function with the concatenate function''' diff --git a/myhdl/test/conversion/general/test_interfaces1.py b/myhdl/test/conversion/general/test_interfaces1.py index f09f909b..eda454f4 100644 --- a/myhdl/test/conversion/general/test_interfaces1.py +++ b/myhdl/test/conversion/general/test_interfaces1.py @@ -13,7 +13,7 @@ class MyIntf(object): self.x = Signal(intbv(2,min=0,max=16)) self.y = Signal(intbv(3,min=0,max=18)) -@myhdl.module +@block def m_one_level(clock,reset,ia,ib): @always_seq(clock.posedge,reset=reset) @@ -23,7 +23,7 @@ def m_one_level(clock,reset,ia,ib): return rtl -@myhdl.module +@block def m_two_level(clock,reset,ia,ib): ic,ie = (MyIntf(),MyIntf(),) @@ -35,7 +35,7 @@ def m_two_level(clock,reset,ia,ib): return g_one, rtl -@myhdl.module +@block def c_testbench_one(): clock = Signal(bool(0)) reset = ResetSignal(0,active=0,async=True) @@ -67,7 +67,7 @@ def c_testbench_one(): return tb_dut, tb_clk, tb_stim -@myhdl.module +@block def c_testbench_two(): clock = Signal(bool(0)) reset = ResetSignal(0,active=0,async=True) diff --git a/myhdl/test/conversion/general/test_interfaces2.py b/myhdl/test/conversion/general/test_interfaces2.py index 4ba8cf37..48661061 100644 --- a/myhdl/test/conversion/general/test_interfaces2.py +++ b/myhdl/test/conversion/general/test_interfaces2.py @@ -12,7 +12,7 @@ class Intf(object): self.y = Signal(intbv(2,min=-2211,max=2211)) self.z = Signal(intbv(3,min=-3311,max=3311)) -@myhdl.module +@block def m_modify(clock,reset,a): intfa = Intf() @@ -31,7 +31,7 @@ def m_modify(clock,reset,a): return rtl_inc,rtl_add -@myhdl.module +@block def m_test_intf(clock,reset,a,b,c): intfa = Intf() @@ -62,7 +62,7 @@ def m_test_intf(clock,reset,a,b,c): return gen_mod,rtl_inc,rtl_combine -@myhdl.module +@block def name_conflict_after_replace(clock, reset, a, a_x): a_x_0 = [Signal(intbv(0)[len(a_x):]) for i in range(8)] @@ -81,7 +81,7 @@ def test_name_conflict_after_replace(): a_x = Signal(intbv(0)[len(a.x):]) assert conversion.analyze(name_conflict_after_replace(clock, reset, a, a_x)) == 0 -@myhdl.module +@block def c_testbench(): clock = Signal(bool(0)) reset = ResetSignal(0, active=0, async=False) diff --git a/myhdl/test/conversion/general/test_interfaces3.py b/myhdl/test/conversion/general/test_interfaces3.py index 664f7b96..a9da68e6 100644 --- a/myhdl/test/conversion/general/test_interfaces3.py +++ b/myhdl/test/conversion/general/test_interfaces3.py @@ -44,14 +44,14 @@ class IntfWithConstant2: self.more_constants = IntfWithConstant1() -@myhdl.module +@block def m_assign(y, x): @always_comb def assign(): y.next = x return assign -@myhdl.module +@block def m_top_assign(x,y,z): """ This module does not test top-level interfaces, @@ -65,14 +65,14 @@ def m_top_assign(x,y,z): return ga1, ga2, gm1 -@myhdl.module +@block def m_assign_intf(x, y): @always_comb def rtl(): x.x.next = y.y return rtl -@myhdl.module +@block def c_testbench_one(): x,y,z = [Signal(intbv(0, min=-8, max=8)) for _ in range(3)] @@ -87,7 +87,7 @@ def c_testbench_one(): return tb_dut, tb_stim -@myhdl.module +@block def m_top_multi_comb(x,y,z): """ This module does not test top-level interfaces, @@ -100,14 +100,14 @@ def m_top_multi_comb(x,y,z): gm = m_multi_comb(*intf) return gm -@myhdl.module +@block def m_multi_comb(x, y, z): @always_comb def rtl(): x.x.next = y.y + z.z.z return rtl -@myhdl.module +@block def c_testbench_two(): x,y,z = [Signal(intbv(0, min=-8, max=8)) for _ in range(3)] @@ -123,7 +123,7 @@ def c_testbench_two(): return tb_dut, tb_stim -@myhdl.module +@block def m_top_const(clock, reset, x, y, intf): @always_seq(clock.posedge, reset=reset) @@ -138,7 +138,7 @@ def m_top_const(clock, reset, x, y, intf): return rtl1, rtl2 -@myhdl.module +@block def c_testbench_three(): """ this will test the use of constants in an inteface diff --git a/myhdl/test/conversion/general/test_interfaces4.py b/myhdl/test/conversion/general/test_interfaces4.py index 3ad0c08e..460211f8 100644 --- a/myhdl/test/conversion/general/test_interfaces4.py +++ b/myhdl/test/conversion/general/test_interfaces4.py @@ -32,7 +32,7 @@ class Intf2(object): self.sig3 = Signal(modbv(0)[8:]) self.intf = Intf1() -@myhdl.module +@block def mod1(clock, reset, intf1, intf2): sig1 = Signal(bool(0)) @@ -53,7 +53,7 @@ def mod1(clock, reset, intf1, intf2): return proc -@myhdl.module +@block def mod2(clock, reset, intf1, intf2): @always_seq(clock.posedge, reset) def proc(): @@ -70,7 +70,7 @@ def mod2(clock, reset, intf1, intf2): return proc -@myhdl.module +@block def m_top(clock, reset, sdi, sdo): intf1 = Intf1() @@ -90,7 +90,7 @@ def m_top(clock, reset, sdi, sdo): return g1, g2, assigns -@myhdl.module +@block def c_testbench_one(): """ yet another interface test. This test is used to expose a particular bug that was discovered diff --git a/myhdl/test/conversion/general/test_listofsigs.py b/myhdl/test/conversion/general/test_listofsigs.py index 5eaf4ce0..ac9195cd 100644 --- a/myhdl/test/conversion/general/test_listofsigs.py +++ b/myhdl/test/conversion/general/test_listofsigs.py @@ -10,7 +10,7 @@ M= 2**N ### A first case that already worked with 5.0 list of signal constraints ### -@myhdl.module +@block def intbv2list(): """Conversion between intbv and list of boolean signals.""" @@ -47,7 +47,7 @@ def test_intbv2list(): ### A number of cases with relaxed constraints, for various decorator types ### -@myhdl.module +@block def inv1(z, a): @always(a) def logic(): @@ -55,7 +55,7 @@ def inv1(z, a): return logic -@myhdl.module +@block def inv2(z, a): @always_comb def logic(): @@ -63,7 +63,7 @@ def inv2(z, a): return logic -@myhdl.module +@block def inv3(z, a): @instance def logic(): @@ -72,7 +72,7 @@ def inv3(z, a): z.next = not a return logic -@myhdl.module +@block def inv4(z, a): @instance def logic(): @@ -83,7 +83,7 @@ def inv4(z, a): return logic -@myhdl.module +@block def case1(z, a, inv): b = [Signal(bool(1)) for i in range(len(a))] c = [Signal(bool(0)) for i in range(len(a))] @@ -104,7 +104,7 @@ def case1(z, a, inv): return extract, inst, assemble -@myhdl.module +@block def case2(z, a, inv): b = [Signal(bool(1)) for i in range(len(a))] c = [Signal(bool(0)) for i in range(len(a))] @@ -125,7 +125,7 @@ def case2(z, a, inv): return extract, inst, assemble -@myhdl.module +@block def case3(z, a, inv): b = [Signal(bool(1)) for i in range(len(a))] c = [Signal(bool(0)) for i in range(len(a))] @@ -150,7 +150,7 @@ def case3(z, a, inv): return extract, inst, assemble -@myhdl.module +@block def case4(z, a, inv): b = [Signal(bool(1)) for i in range(len(a))] c = [Signal(bool(0)) for i in range(len(a))] @@ -181,7 +181,7 @@ def case4(z, a, inv): -@myhdl.module +@block def processlist(case, inv): """Extract list from intbv, do some processing, reassemble.""" @@ -223,7 +223,7 @@ def test_processlist44(): # signed and unsigned -@myhdl.module +@block def unsigned(): z = Signal(intbv(0)[8:]) a = [Signal(intbv(0)[8:]) for i in range(3)] @@ -246,7 +246,7 @@ def test_unsigned(): conversion.verify(unsigned()) -@myhdl.module +@block def signed(): z = Signal(intbv(0, min=-10, max=34)) a = [Signal(intbv(0, min=-5, max=17)) for i in range(3)] @@ -269,7 +269,7 @@ def test_signed(): conversion.verify(signed()) -@myhdl.module +@block def mixed(): z = Signal(intbv(0, min=0, max=34)) a = [Signal(intbv(0, min=-11, max=17)) for i in range(3)] @@ -297,7 +297,7 @@ def test_mixed(): # port in list -@myhdl.module +@block def portInList(z, a, b): m = [a, b] @@ -322,7 +322,7 @@ def test_portInList(): # signal in multiple lists -@myhdl.module +@block def sigInMultipleLists(): z, a, b = [Signal(intbv(0)[8:]) for i in range(3)] @@ -347,7 +347,7 @@ def test_sigInMultipleLists(): # list of signals as port -@myhdl.module +@block def my_register(clk, inp, outp): @always(clk.posedge) def my_register_impl(): diff --git a/myhdl/test/conversion/general/test_loops.py b/myhdl/test/conversion/general/test_loops.py index 115e6d2b..7438b9f1 100644 --- a/myhdl/test/conversion/general/test_loops.py +++ b/myhdl/test/conversion/general/test_loops.py @@ -10,7 +10,7 @@ from myhdl.conversion import verify, analyze from myhdl import ConversionError from myhdl.conversion._misc import _error -@myhdl.module +@block def ForLoopError1(a, out): @instance def logic(): @@ -23,7 +23,7 @@ def ForLoopError1(a, out): out.next = var return logic -@myhdl.module +@block def ForLoopError2(a, out): @instance def logic(): @@ -36,7 +36,7 @@ def ForLoopError2(a, out): out.next = var return logic -@myhdl.module +@block def ForLoop1(a, out): @instance def logic(): @@ -49,7 +49,7 @@ def ForLoop1(a, out): out.next = var return logic -@myhdl.module +@block def ForLoop2(a, out): @instance def logic(): @@ -62,7 +62,7 @@ def ForLoop2(a, out): out.next = var return logic -@myhdl.module +@block def ForLoop3(a, out): @instance def logic(): @@ -75,7 +75,7 @@ def ForLoop3(a, out): out.next = var return logic -@myhdl.module +@block def ForLoop4(a, out): @instance def logic(): @@ -88,7 +88,7 @@ def ForLoop4(a, out): out.next = var return logic -@myhdl.module +@block def ForLoop5(a, out): @instance def logic(): @@ -101,7 +101,7 @@ def ForLoop5(a, out): out.next = var return logic -@myhdl.module +@block def ForLoop6(a, out): @instance def logic(): @@ -114,7 +114,7 @@ def ForLoop6(a, out): out.next = var return logic -@myhdl.module +@block def ForContinueLoop(a, out): @instance def logic(): @@ -128,7 +128,7 @@ def ForContinueLoop(a, out): out.next = var return logic -@myhdl.module +@block def ForBreakLoop(a, out): @instance def logic(): @@ -141,7 +141,7 @@ def ForBreakLoop(a, out): break return logic -@myhdl.module +@block def ForBreakContinueLoop(a, out): @instance def logic(): @@ -155,7 +155,7 @@ def ForBreakContinueLoop(a, out): break return logic -@myhdl.module +@block def NestedForLoop1(a, out): @instance def logic(): @@ -173,7 +173,7 @@ def NestedForLoop1(a, out): out.next = var return logic -@myhdl.module +@block def NestedForLoop2(a, out): @instance def logic(): @@ -200,7 +200,7 @@ def ReturnFromFunction(a): return i return 0 -@myhdl.module +@block def FunctionCall(a, out): @instance def logic(): @@ -219,7 +219,7 @@ def ReturnFromTask(a, out): return out[:] = 23 # to notice it -@myhdl.module +@block def TaskCall(a, out): @instance def logic(): @@ -230,7 +230,7 @@ def TaskCall(a, out): out.next = var return logic -@myhdl.module +@block def WhileLoop(a, out): @instance def logic(): @@ -245,7 +245,7 @@ def WhileLoop(a, out): out.next = var return logic -@myhdl.module +@block def WhileContinueLoop(a, out): @instance def logic(): @@ -262,7 +262,7 @@ def WhileContinueLoop(a, out): out.next = var return logic -@myhdl.module +@block def WhileBreakLoop(a, out): @instance def logic(): @@ -278,7 +278,7 @@ def WhileBreakLoop(a, out): i -= 1 return logic -@myhdl.module +@block def WhileBreakContinueLoop(a, out): @instance def logic(): @@ -295,7 +295,7 @@ def WhileBreakContinueLoop(a, out): break return logic -@myhdl.module +@block def LoopBench(LoopTest): a = Signal(intbv(-1)[16:]) diff --git a/myhdl/test/conversion/general/test_method.py b/myhdl/test/conversion/general/test_method.py index 022032ce..7f648376 100644 --- a/myhdl/test/conversion/general/test_method.py +++ b/myhdl/test/conversion/general/test_method.py @@ -8,7 +8,7 @@ class HdlObj(object): def __init__(self): pass - @myhdl.module + @block def method_func(self, clk, srst, x, y): z = Signal(intbv(0, min=y.min, max=y.max)) ifx = self._mfunc(x, z) @@ -21,14 +21,14 @@ class HdlObj(object): return hdl, ifx - @myhdl.module + @block def _mfunc(self, x, y): @always_comb def _hdl(): y.next = x + 1 return _hdl -@myhdl.module +@block def _func(x,y): @always_comb def _hdl(): @@ -39,7 +39,7 @@ class HdlObjObj(object): def __init__(self): pass - @myhdl.module + @block def method_func(self, clk, srst, x, y): z1 = Signal(intbv(0, min=y.min, max=y.max)) z2 = Signal(intbv(0, min=y.min, max=y.max)) @@ -60,7 +60,7 @@ class HdlObjAttrSimple(object): def __init__(self): self.AConstant = 3 - @myhdl.module + @block def method_func(self, clk, srst, x, y): # limitation for class method conversion, the object attributes @@ -84,7 +84,7 @@ class HdlObjAttr(object): self.z = Signal(intbv(0, min=y.min, max=y.max)) self.hobj = HdlObj() - @myhdl.module + @block def method_func(self): ifx = self.hobj._mfunc(self.x, self.z) @always(self.clk.posedge) @@ -96,7 +96,7 @@ class HdlObjAttr(object): return hdl, ifx -@myhdl.module +@block def ObjBench(hObj): clk = Signal(False) diff --git a/myhdl/test/conversion/general/test_numass.py b/myhdl/test/conversion/general/test_numass.py index e6dfdc3d..9f1e221b 100644 --- a/myhdl/test/conversion/general/test_numass.py +++ b/myhdl/test/conversion/general/test_numass.py @@ -5,7 +5,7 @@ import myhdl from myhdl import * -@myhdl.module +@block def NumassBench(): p = Signal(intbv(1)[8:]) diff --git a/myhdl/test/conversion/general/test_ram.py b/myhdl/test/conversion/general/test_ram.py index d0fb48a7..da6e7d6d 100644 --- a/myhdl/test/conversion/general/test_ram.py +++ b/myhdl/test/conversion/general/test_ram.py @@ -6,7 +6,7 @@ import unittest import myhdl from myhdl import * -@myhdl.module +@block def ram1(dout, din, addr, we, clk, depth=128): """ Simple ram model """ @@ -22,7 +22,7 @@ def ram1(dout, din, addr, we, clk, depth=128): dout.next = mem[int(addr)] return logic -@myhdl.module +@block def ram_clocked(dout, din, addr, we, clk, depth=128): """ Ram model """ @@ -38,7 +38,7 @@ def ram_clocked(dout, din, addr, we, clk, depth=128): return access -@myhdl.module +@block def ram_deco1(dout, din, addr, we, clk, depth=128): """ Ram model """ @@ -58,7 +58,7 @@ def ram_deco1(dout, din, addr, we, clk, depth=128): return write, read -@myhdl.module +@block def ram_deco2(dout, din, addr, we, clk, depth=128): """ Ram model """ @@ -76,7 +76,7 @@ def ram_deco2(dout, din, addr, we, clk, depth=128): return write, read -@myhdl.module +@block def ram2(dout, din, addr, we, clk, depth=128): memL = [Signal(intbv()[len(dout):]) for i in range(depth)] @@ -97,7 +97,7 @@ def ram2(dout, din, addr, we, clk, depth=128): return wrLogic, rdLogic -@myhdl.module +@block def RamBench(ram, depth=128): dout = Signal(intbv(0)[8:]) diff --git a/myhdl/test/conversion/general/test_randscrambler.py b/myhdl/test/conversion/general/test_randscrambler.py index cd4a2392..031ea6e2 100644 --- a/myhdl/test/conversion/general/test_randscrambler.py +++ b/myhdl/test/conversion/general/test_randscrambler.py @@ -17,7 +17,7 @@ N = 8 M = 2 ** N DEPTH = 5 -@myhdl.module +@block def xor(z, a, b, c): @instance def logic(): @@ -32,7 +32,7 @@ def randOthers(i, n): random.shuffle(l) return l[0], l[1] -@myhdl.module +@block def randscrambler(ol, il, stage=0): """ Recursive hierarchy of random xor gates. @@ -60,7 +60,7 @@ def randscrambler(ol, il, stage=0): i1[i] = xor(ol[i], il[i], il[j], il[k]) return i1 -@myhdl.module +@block def randscrambler_top(o7, o6, o5, o4, o3, o2, o1, o0, i7, i6, i5, i4, i3, i2, i1, i0): sl1 = [i7, i6, i5, i4, i3, i2, i1, i0] @@ -72,7 +72,7 @@ o7, o6, o5, o4, o3, o2, o1, o0 = [Signal(bool()) for i in range(N)] i7, i6, i5, i4, i3, i2, i1, i0 = [Signal(bool()) for i in range(N)] v7, v6, v5, v4, v3, v2, v1, v0 = [Signal(bool()) for i in range(N)] -@myhdl.module +@block def randscramblerBench(): @instance diff --git a/myhdl/test/conversion/general/test_rom.py b/myhdl/test/conversion/general/test_rom.py index fbf27050..48fa5949 100644 --- a/myhdl/test/conversion/general/test_rom.py +++ b/myhdl/test/conversion/general/test_rom.py @@ -10,7 +10,7 @@ D = 256 ROM = tuple([randrange(D) for i in range(D)]) -@myhdl.module +@block def rom1(dout, addr, clk): @instance @@ -21,7 +21,7 @@ def rom1(dout, addr, clk): return rdLogic -@myhdl.module +@block def rom2(dout, addr, clk): theROM = ROM @@ -34,7 +34,7 @@ def rom2(dout, addr, clk): return rdLogic -@myhdl.module +@block def rom3(dout, addr, clk): @@ -48,7 +48,7 @@ def rom3(dout, addr, clk): return rdLogic -@myhdl.module +@block def rom4(dout, addr, clk): @always_comb @@ -58,7 +58,7 @@ def rom4(dout, addr, clk): return read -@myhdl.module +@block def RomBench(rom): dout = Signal(intbv(0)[8:]) diff --git a/myhdl/test/conversion/general/test_set_dir.py b/myhdl/test/conversion/general/test_set_dir.py index 94456fe9..842505db 100644 --- a/myhdl/test/conversion/general/test_set_dir.py +++ b/myhdl/test/conversion/general/test_set_dir.py @@ -9,7 +9,7 @@ import myhdl _version = myhdl.__version__.replace('.','') _shortversion = _version.replace('dev','') -@myhdl.module +@block def simple_dir_model(din, dout, clk): """ Simple convertible model """ diff --git a/myhdl/test/conversion/general/test_ternary.py b/myhdl/test/conversion/general/test_ternary.py index 2c60c00e..305234f6 100644 --- a/myhdl/test/conversion/general/test_ternary.py +++ b/myhdl/test/conversion/general/test_ternary.py @@ -6,7 +6,7 @@ import unittest import myhdl from myhdl import * -@myhdl.module +@block def ternary1(dout, clk, rst): @always(clk.posedge, rst.negedge) @@ -19,7 +19,7 @@ def ternary1(dout, clk, rst): return logic -@myhdl.module +@block def ternary2(dout, clk, rst): dout_d = Signal(intbv(0)[len(dout):]) @@ -37,7 +37,7 @@ def ternary2(dout, clk, rst): return logic, comb -@myhdl.module +@block def TernaryBench(ternary): dout = Signal(intbv(0)[8:]) diff --git a/myhdl/test/conversion/general/test_toplevel_method.py b/myhdl/test/conversion/general/test_toplevel_method.py index 8322e0bc..1ed6704c 100644 --- a/myhdl/test/conversion/general/test_toplevel_method.py +++ b/myhdl/test/conversion/general/test_toplevel_method.py @@ -10,7 +10,7 @@ class HdlObj(object): def __init__(self): pass - @myhdl.module + @block def method_func(self, clk, srst, x, y): z = Signal(intbv(0, min=y.min, max=y.max)) ifx = self._mfunc(x, z) @@ -23,14 +23,14 @@ class HdlObj(object): return hdl, ifx - @myhdl.module + @block def _mfunc(self, x, y): @always_comb def _hdl(): y.next = x + 1 return _hdl -@myhdl.module +@block def _func(x,y): @always_comb def _hdl(): @@ -40,15 +40,15 @@ def _func(x,y): class HdlObjObj(object): def __init__(self): pass - - @myhdl.module + + @block def method_func(self, clk, srst, x, y): z1 = Signal(intbv(0, min=y.min, max=y.max)) z2 = Signal(intbv(0, min=y.min, max=y.max)) hobj = HdlObj() ifx1 = hobj._mfunc(x, z1) ifx2 = _func(x, z2) - + @always(clk.posedge) def hdl(): if srst: @@ -56,15 +56,15 @@ class HdlObjObj(object): else: y.next = x + z1 + (z1 - z2) - return hdl, ifx1, ifx2 + return hdl, ifx1, ifx2 class HdlObjAttrSimple(object): def __init__(self): self.Constant = 3 - @myhdl.module + @block def method_func(self, clk, srst, x, y): - + # limitation for class method conversion, the object attributes # can only be used/accessed during elaboration. Constant = int(self.Constant) @@ -73,7 +73,7 @@ class HdlObjAttrSimple(object): if srst: y.next = 0 else: - y.next = x + (x+1) + Constant - 3 + y.next = x + (x+1) + Constant - 3 return hdl @@ -82,7 +82,7 @@ class HdlObjNotSelf(object): def __init__(this): pass - @myhdl.module + @block def method_func(this, clk, srst, x, y): @always(clk.posedge) @@ -127,6 +127,3 @@ def test_hdlobjnotself(): y = Signal(intbv(0, min=0, max=16)) hdlobj_inst = HdlObjNotSelf() analyze(hdlobj_inst.method_func(clk, x, srst, y)) - - - diff --git a/myhdl/test/conversion/toVHDL/test_custom.py b/myhdl/test/conversion/toVHDL/test_custom.py index 1d2542ed..0b12d5a3 100644 --- a/myhdl/test/conversion/toVHDL/test_custom.py +++ b/myhdl/test/conversion/toVHDL/test_custom.py @@ -15,7 +15,7 @@ from myhdl.conversion._misc import _error ACTIVE_LOW, INACTIVE_HIGH = 0, 1 -@myhdl.module +@block def incRef(count, enable, clock, reset, n): """ Incrementer with enable. @@ -37,7 +37,7 @@ def incRef(count, enable, clock, reset, n): return logic -@myhdl.module +@block def incGen(count, enable, clock, reset, n): """ Generator with vhdl_code is not permitted """ @instance @@ -53,7 +53,7 @@ def incGen(count, enable, clock, reset, n): return logic -@myhdl.module +@block def inc(count, enable, clock, reset, n): """ Incrementer with enable. @@ -92,7 +92,7 @@ end process; -@myhdl.module +@block def incErr(count, enable, clock, reset, n): @always(clock.posedge, reset.negedge) @@ -125,7 +125,7 @@ end -@myhdl.module +@block def inc_comb(nextCount, count, n): @always_comb @@ -143,7 +143,7 @@ $nextCount <= ($count + 1) mod $n; return logic -@myhdl.module +@block def inc_seq(count, nextCount, enable, clock, reset): @always(clock.posedge, reset.negedge) @@ -173,7 +173,7 @@ end process; return logic -@myhdl.module +@block def inc2(count, enable, clock, reset, n): nextCount = Signal(intbv(0, min=0, max=n)) @@ -184,13 +184,13 @@ def inc2(count, enable, clock, reset, n): return comb, seq -@myhdl.module +@block def inc3(count, enable, clock, reset, n): inc2_inst = inc2(count, enable, clock, reset, n) return inc2_inst -@myhdl.module +@block def clockGen(clock): @instance def logic(): @@ -204,7 +204,7 @@ NRTESTS = 1000 ENABLES = tuple([min(1, randrange(5)) for i in range(NRTESTS)]) -@myhdl.module +@block def stimulus(enable, clock, reset): @instance def logic(): @@ -223,7 +223,7 @@ def stimulus(enable, clock, reset): return logic -@myhdl.module +@block def check(count, enable, clock, reset, n): @instance def logic(): @@ -241,7 +241,7 @@ def check(count, enable, clock, reset, n): print(count) return logic -@myhdl.module +@block def customBench(inc): m = 8 diff --git a/myhdl/test/conversion/toVerilog/test_RandomScrambler.py b/myhdl/test/conversion/toVerilog/test_RandomScrambler.py index 548c6493..d4f804d8 100644 --- a/myhdl/test/conversion/toVerilog/test_RandomScrambler.py +++ b/myhdl/test/conversion/toVerilog/test_RandomScrambler.py @@ -17,7 +17,7 @@ N = 8 M = 2 ** N DEPTH = 5 -@myhdl.module +@block def XorGate(z, a, b, c): @instance def logic(): @@ -32,7 +32,7 @@ def randOthers(i, n): random.shuffle(l) return l[0], l[1] -@myhdl.module +@block def RandomScramblerModule(ol, il, stage=0): """ Recursive hierarchy of random xor gates. @@ -60,7 +60,7 @@ def RandomScramblerModule(ol, il, stage=0): i1[i] = XorGate(ol[i], il[i], il[j], il[k]) return i1 -@myhdl.module +@block def RandomScrambler(o7, o6, o5, o4, o3, o2, o1, o0, i7, i6, i5, i4, i3, i2, i1, i0): sl1 = [i7, i6, i5, i4, i3, i2, i1, i0] diff --git a/myhdl/test/conversion/toVerilog/test_custom.py b/myhdl/test/conversion/toVerilog/test_custom.py index c9d4cc19..800f320b 100644 --- a/myhdl/test/conversion/toVerilog/test_custom.py +++ b/myhdl/test/conversion/toVerilog/test_custom.py @@ -18,7 +18,7 @@ from myhdl.conversion._misc import _error ACTIVE_LOW, INACTIVE_HIGH = 0, 1 -@myhdl.module +@block def incRef(count, enable, clock, reset, n): """ Incrementer with enable. @@ -40,7 +40,7 @@ def incRef(count, enable, clock, reset, n): return logic -@myhdl.module +@block def incGen(count, enable, clock, reset, n): """ Generator with verilog_code is not permitted """ @instance @@ -56,7 +56,7 @@ def incGen(count, enable, clock, reset, n): return logic -@myhdl.module +@block def inc(count, enable, clock, reset, n): """ Incrementer with enable. @@ -95,7 +95,7 @@ end return incProcess -@myhdl.module +@block def incErr(count, enable, clock, reset, n): @always(clock.posedge, reset.negedge) @@ -128,7 +128,7 @@ end -@myhdl.module +@block def inc_comb(nextCount, count, n): @always_comb @@ -146,7 +146,7 @@ assign $nextCount = ($count + 1) % $n; return logic -@myhdl.module +@block def inc_seq(count, nextCount, enable, clock, reset): @always(clock.posedge, reset.negedge) @@ -176,7 +176,7 @@ end """ return logic -@myhdl.module +@block def inc2(count, enable, clock, reset, n): nextCount = Signal(intbv(0, min=0, max=n)) @@ -187,7 +187,7 @@ def inc2(count, enable, clock, reset, n): return comb, seq -@myhdl.module +@block def inc3(count, enable, clock, reset, n): inc2_inst = inc2(count, enable, clock, reset, n) return inc2_inst diff --git a/myhdl/test/core/test_traceSignals.py b/myhdl/test/core/test_traceSignals.py index a65d5032..23c557d7 100644 --- a/myhdl/test/core/test_traceSignals.py +++ b/myhdl/test/core/test_traceSignals.py @@ -25,8 +25,7 @@ import random import pytest -import myhdl -from myhdl import Signal, Simulation, _simulator, delay, instance, intbv +from myhdl import block, Signal, Simulation, _simulator, delay, instance, intbv from myhdl._traceSignals import TraceSignalsError, _error, traceSignals from helpers import raises_kind @@ -36,7 +35,7 @@ path = os.path QUIET=1 -@myhdl.module +@block def gen(clk): @instance def logic(): @@ -45,37 +44,37 @@ def gen(clk): clk.next = not clk return logic -@myhdl.module +@block def fun(): clk = Signal(bool(0)) inst = gen(clk) return inst -@myhdl.module +@block def dummy(): clk = Signal(bool(0)) inst = gen(clk) return 1 -@myhdl.module +@block def top(): inst = traceSignals(fun()) return inst -@myhdl.module +@block def top2(): inst = [{} for i in range(4)] j = 3 inst[j-2]['key'] = traceSignals(fun()) return inst -@myhdl.module +@block def top3(): inst_1 = traceSignals(fun()) inst_2 = traceSignals(fun()) return inst_1, inst_2 -@myhdl.module +@block def genTristate(clk, x, y, z): xd = x.driver() yd = y.driver() @@ -100,7 +99,7 @@ def genTristate(clk, x, y, z): yd.next = zd.next = 0 return ckgen,logic -@myhdl.module +@block def tristate(): from myhdl import TristateSignal clk = Signal(bool(0)) @@ -111,7 +110,7 @@ def tristate(): inst = genTristate(clk, x, y, z) return inst -@myhdl.module +@block def topTristate(): inst = traceSignals(tristate()) return inst