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mirror of https://github.com/myhdl/myhdl.git synced 2025-01-24 21:52:56 +08:00

always comb with sets

This commit is contained in:
jand 2003-10-02 08:52:33 +00:00
parent 1b25d63a1a
commit b4891aac87
5 changed files with 21 additions and 26 deletions

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@ -65,7 +65,7 @@ class Signal(object):
__slots__ = ('_next', '_val', '_min', '_max', '_type',
'_eventWaiters', '_posedgeWaiters', '_negedgeWaiters',
'_code', '_tracing', '_nrbits', '_checkVal', '_setNextVal',
'_printVcd', '_info',
'_printVcd', '_driven', '_name'
)
def __new__(cls, val=None, delay=None):
@ -84,7 +84,7 @@ class Signal(object):
"""
self._next = self._val = val
self._min = self._max = None
self._min = self._max = self._name = self._driven = None
self._nrbits = 0
self._printVcd = self._printVcdStr
if type(val) is bool:

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@ -30,7 +30,6 @@ negedge -- callable to model a falling edge on a signal in a yield statement
join -- callable to join clauses in a yield statement
intbv -- mutable integer class with bit vector facilities
downrange -- function that returns a downward range
Error -- myhdl Error exception
bin -- returns a binary string representation.
The optional width specifies the desired string
width: padding of the sign-bit is used.
@ -57,11 +56,12 @@ from _join import join
from _Signal import posedge, negedge, Signal
from _simulator import now
from _delay import delay
from _util import downrange, Error, StopSimulation
from _util import downrange, StopSimulation
from _Cosimulation import Cosimulation
from _Simulation import Simulation
from _misc import instances, processes
from _always_comb import always_comb
from _enum import enum
from _traceSignals import traceSignals
from _toVerilog import toVerilog

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@ -29,6 +29,7 @@ import sys
import inspect
from types import FunctionType
import compiler
from sets import Set
from myhdl import Signal
from myhdl._util import _isgeneratorfunction
@ -74,7 +75,9 @@ def always_comb(func):
sigdict = {}
for dict in (f.f_locals, f.f_globals):
for n, v in dict.items():
if isinstance(v, Signal) and n not in varnames:
if isinstance(v, Signal) and \
n not in varnames and \
n not in sigdict:
sigdict[n] = v
c = _AlwaysComb(func, sigdict)
return c.genfunc()
@ -84,8 +87,8 @@ INPUT, OUTPUT, INOUT = range(3)
class _SigNameVisitor(object):
def __init__(self, sigdict):
self.inputs = []
self.outputs = []
self.inputs = Set()
self.outputs = Set()
self.toplevel = 1
self.sigdict = sigdict
@ -108,9 +111,9 @@ class _SigNameVisitor(object):
if node.name not in self.sigdict:
return
if access == INPUT:
self.inputs.append(node.name)
self.inputs.add(node.name)
elif access == OUTPUT:
self.outputs.append(node.name)
self.outputs.add(node.name)
elif access == INOUT:
raise SignalAsInoutError(node.name)
else:
@ -157,8 +160,6 @@ class _AlwaysComb(object):
tree = compiler.parse(s)
v = _SigNameVisitor(sigdict)
compiler.walk(tree, v)
v.inputs.sort()
v.outputs.sort()
self.inputs = v.inputs
self.outputs = v.outputs

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@ -69,8 +69,6 @@ def bin(num, width=0):
pad = '1'
return (width - len(s)) * pad + s
class Error(Exception):
pass
class StopSimulation(exceptions.Exception):
""" Basic exception to stop a Simulation """

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@ -31,6 +31,7 @@ random.seed(1) # random, but deterministic
import unittest
from unittest import TestCase
import inspect
from sets import Set
from myhdl import Signal, Simulation, instances, processes, \
intbv, posedge, negedge, delay, StopSimulation
@ -95,7 +96,7 @@ class AlwaysCombCompilationTest(TestCase):
v = u
g = always_comb(h)
i = g.gi_frame.f_locals['self']
expected = ['a']
expected = Set(['a'])
self.assertEqual(i.inputs, expected)
def testInfer2(self):
@ -106,8 +107,7 @@ class AlwaysCombCompilationTest(TestCase):
g = a
g = always_comb(h)
i = g.gi_frame.f_locals['self']
expected = ['a', 'x']
expected.sort()
expected = Set(['a', 'x'])
self.assertEqual(i.inputs, expected)
def testInfer3(self):
@ -119,7 +119,7 @@ class AlwaysCombCompilationTest(TestCase):
a = 1
g = always_comb(h)
i = g.gi_frame.f_locals['self']
expected = ['x']
expected = Set(['x'])
self.assertEqual(i.inputs, expected)
def testInfer4(self):
@ -130,7 +130,7 @@ class AlwaysCombCompilationTest(TestCase):
x = 1
g = always_comb(h)
i = g.gi_frame.f_locals['self']
expected = ['a']
expected = Set(['a'])
self.assertEqual(i.inputs, expected)
@ -164,8 +164,7 @@ class AlwaysCombCompilationTest(TestCase):
c.next[a:0] = x[b:0]
g = always_comb(h)
i = g.gi_frame.f_locals['self']
expected = ['a', 'b', 'x']
expected.sort()
expected = Set(['a', 'b', 'x'])
self.assertEqual(i.inputs, expected)
def testInfer8(self):
@ -176,8 +175,7 @@ class AlwaysCombCompilationTest(TestCase):
c.next[8:1+a+v] = x[4:b*3+u]
g = always_comb(h)
i = g.gi_frame.f_locals['self']
expected = ['a', 'b', 'x']
expected.sort()
expected = Set(['a', 'b', 'x'])
self.assertEqual(i.inputs, expected)
def testInfer9(self):
@ -186,8 +184,7 @@ class AlwaysCombCompilationTest(TestCase):
c.next[a-1] = x[b-1]
g = always_comb(h)
i = g.gi_frame.f_locals['self']
expected = ['a', 'b', 'x']
expected.sort()
expected = Set(['a', 'b', 'x'])
self.assertEqual(i.inputs, expected)
def testInfer10(self):
@ -198,8 +195,7 @@ class AlwaysCombCompilationTest(TestCase):
c.next = f(a, 2*b, d*x)
g = always_comb(h)
i = g.gi_frame.f_locals['self']
expected = ['a', 'b', 'd', 'x']
expected.sort()
expected = Set(['a', 'b', 'd', 'x'])
self.assertEqual(i.inputs, expected)
def testEmbeddedFunction(self):