From b5f9ddfec3eb53f5127c7a3c4ad29a6b68ceda09 Mon Sep 17 00:00:00 2001 From: jand Date: Mon, 19 Jan 2004 22:12:03 +0000 Subject: [PATCH] random scrambler --- myhdl/_extractHierarchy.py | 1 - myhdl/_toVerilog/_analyze.py | 9 +- myhdl/_toVerilog/_convert.py | 1 + myhdl/test/toVerilog/test_RandomScrambler.py | 152 +++++++++++++++++++ myhdl/test/toVerilog/test_all.py | 7 +- 5 files changed, 165 insertions(+), 5 deletions(-) create mode 100644 myhdl/test/toVerilog/test_RandomScrambler.py diff --git a/myhdl/_extractHierarchy.py b/myhdl/_extractHierarchy.py index f4593d1e..a5aafee2 100644 --- a/myhdl/_extractHierarchy.py +++ b/myhdl/_extractHierarchy.py @@ -175,7 +175,6 @@ class _HierExtr(object): gens = _getGens(arg) for gname, g in frame.f_locals.items(): if type(g) is _AlwaysComb: - print "YES" g = g.gen if type(g) is GeneratorType and \ g in gens and gname not in instNames: diff --git a/myhdl/_toVerilog/_analyze.py b/myhdl/_toVerilog/_analyze.py index 9b43a42e..b065ceb2 100644 --- a/myhdl/_toVerilog/_analyze.py +++ b/myhdl/_toVerilog/_analyze.py @@ -61,9 +61,14 @@ def _analyzeSigs(hierarchy): for n, s in sigdict.items(): if s._name is None: if len(prefixes) > 1: - s._name = '_' + '_'.join(prefixes[1:]) + '_' + n + name = '_' + '_'.join(prefixes[1:]) + '_' + n else: - s._name = n + name = n + if '[' in name or ']' in name: + name = "\\" + name + ' ' +## name = name.replace('[', '_') +## name = name.replace(']', '_') + s._name = name siglist.append(s) if not s._nrbits: raise ToVerilogError(_error.UndefinedBitWidth, s._name) diff --git a/myhdl/_toVerilog/_convert.py b/myhdl/_toVerilog/_convert.py index 90d3b26c..45a295f4 100644 --- a/myhdl/_toVerilog/_convert.py +++ b/myhdl/_toVerilog/_convert.py @@ -565,6 +565,7 @@ class _ConvertVisitor(_ToVerilogMixin): if isinstance(obj, int): self.write(str(obj)) elif type(obj) is Signal: + assert obj._name self.write(obj._name) else: self.write(n) diff --git a/myhdl/test/toVerilog/test_RandomScrambler.py b/myhdl/test/toVerilog/test_RandomScrambler.py new file mode 100644 index 00000000..a65038d5 --- /dev/null +++ b/myhdl/test/toVerilog/test_RandomScrambler.py @@ -0,0 +1,152 @@ +import os +path = os.path +import unittest +from unittest import TestCase +import random +from random import randrange +# random.seed(2) + +from myhdl import * + +N = 8 +M = 2 ** N +DEPTH = 5 + +def XorGate(z, a, b, c): + while 1: + yield a, b, c + z.next = a ^ b ^ c + +def XorGate(z, a, b, c): + def logic(): + while 1: + yield a, b, c + z.next = a ^ b ^ c + return logic() + +def randOthers(i, n): + l = range(n) + l.remove(i) + random.shuffle(l) + return l[0], l[1] + + +def RandomScramblerModule(ol, il, stage=0): + """ Recursive hierarchy of random xor gates. + + An invented module to check hierarchy with toVerilog. + + """ + + sl1 = [Signal(bool()) for i in range(N)] + sl2 = [Signal(bool()) for i in range(N)] + i1 = [None] * N + i2 = [None] * N + + if stage < DEPTH: + for i in range(N): + j, k = randOthers(i, N) + i1[i] = XorGate(sl1[i], il[i], il[j], il[k]) + rs = RandomScramblerModule(sl2, sl1, stage=stage+1) + for i in range(N): + j, k = randOthers(i, N) + i2[i] = XorGate(ol[i], sl2[i], sl2[j], sl2[k]) + return i1, i2, rs + else: + for i in range(N): + j, k = randOthers(i, N) + i1[i] = XorGate(ol[i], il[i], il[j], il[k]) + return i1 + + +def RandomScrambler(o7, o6, o5, o4, o3, o2, o1, o0, + i7, i6, i5, i4, i3, i2, i1, i0): + sl1 = [i7, i6, i5, i4, i3, i2, i1, i0] + sl2 = [o7, o6, o5, o4, o3, o2, o1, o0] + rs = RandomScramblerModule(sl2, sl1, stage=0) + return rs + +o7, o6, o5, o4, o3, o2, o1, o0 = [Signal(bool()) for i in range(N)] +i7, i6, i5, i4, i3, i2, i1, i0 = [Signal(bool()) for i in range(N)] +v7, v6, v5, v4, v3, v2, v1, v0 = [Signal(bool()) for i in range(N)] + + +objfile = "rs.o" +analyze_cmd = "iverilog -o %s rs.v tb_rs.v" % objfile +simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi %s" % objfile + + +def RandomScrambler_v(o7, o6, o5, o4, o3, o2, o1, o0, + i7, i6, i5, i4, i3, i2, i1, i0): + if path.exists(objfile): + os.remove(objfile) + os.system(analyze_cmd) + return Cosimulation(simulate_cmd, **locals()) + + +class TestRandomScramber(TestCase): + + def stimulus(self): + input = intbv() + output = intbv() + output_v = intbv() + for i in range(100): + input[:] = randrange(M) + i7.next = input[7] + i6.next = input[6] + i5.next = input[5] + i4.next = input[4] + i3.next = input[3] + i2.next = input[2] + i1.next = input[1] + i0.next = input[0] + yield delay(10) + output[7] = o7 + output[6] = o6 + output[5] = o5 + output[4] = o4 + output[3] = o3 + output[2] = o2 + output[1] = o1 + output[0] = o0 + output_v[7] = o7 + output_v[6] = o6 + output_v[5] = o5 + output_v[4] = o4 + output_v[3] = o3 + output_v[2] = o2 + output_v[1] = o1 + output_v[0] = o0 +## print output +## print output_v +## print input + self.assertEqual(output, output_v) + + def test(self): + rs = toVerilog(RandomScrambler, + o7, o6, o5, o4, o3, o2, o1, o0, + i7, i6, i5, i4, i3, i2, i1, i0 + ) + rs_v = RandomScrambler_v(v7, v6, v5, v4, v3, v2, v1, v0, + i7, i6, i5, i4, i3, i2, i1, i0 + ) + sim = Simulation(rs, self.stimulus(), rs_v) + sim.run() + +if __name__ == '__main__': + unittest.main() + + + + + + + + + + + + + + + diff --git a/myhdl/test/toVerilog/test_all.py b/myhdl/test/toVerilog/test_all.py index 06285c2d..ce9831c3 100644 --- a/myhdl/test/toVerilog/test_all.py +++ b/myhdl/test/toVerilog/test_all.py @@ -24,10 +24,13 @@ __revision__ = "$Revision$" __date__ = "$Date$" import test_bin2gray, test_inc, test_fsm, test_ops, test_NotSupported, \ - test_inc_initial, test_hec, test_loops, test_infer, test_errors + test_inc_initial, test_hec, test_loops, test_infer, test_errors, \ + test_RandomScrambler + modules = (test_bin2gray, test_inc, test_fsm, test_ops, test_NotSupported, \ - test_inc_initial, test_hec, test_loops, test_infer, test_errors + test_inc_initial, test_hec, test_loops, test_infer, test_errors, \ + test_RandomScrambler ) import unittest