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Merge pull request #133 from clade/0.9-maintenance

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assign statement (constwires) support litterals larger than 32 bits
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jandecaluwe 2015-11-01 20:59:29 +01:00
commit b726eb8139
1 changed files with 3 additions and 1 deletions
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myhdl/conversion/_toVerilog.py
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@ -324,7 +324,9 @@ def _writeSigDecls(f, intf, siglist, memlist):
c = int(s.val) c = int(s.val)
else: else:
raise ToVerilogError("Unexpected type for constant signal", s._name) raise ToVerilogError("Unexpected type for constant signal", s._name)
print("assign %s = %s;" % (s._name, c), file=f) c_len = s._nrbits
c_str = "%s"%c
print("assign %s = %s'd%s;" % (s._name, c_len, c_str), file=f)
print(file=f) print(file=f)
# shadow signal assignments # shadow signal assignments
for s in siglist: for s in siglist: