From b9e332cc5a513ab06defe51cb7fb2af1abbc22c7 Mon Sep 17 00:00:00 2001
From: jand <none@none>
Date: Mon, 2 Feb 2004 16:49:03 +0000
Subject: [PATCH] printing

---
 myhdl/_toVerilog/_analyze.py        |  2 +-
 myhdl/_toVerilog/_convert.py        | 15 ++++++++-------
 myhdl/test/toVerilog/test_errors.py |  3 +++
 3 files changed, 12 insertions(+), 8 deletions(-)

diff --git a/myhdl/_toVerilog/_analyze.py b/myhdl/_toVerilog/_analyze.py
index d695412d..4835c7b7 100644
--- a/myhdl/_toVerilog/_analyze.py
+++ b/myhdl/_toVerilog/_analyze.py
@@ -373,7 +373,7 @@ class _AnalyzeVisitor(_ToVerilogMixin):
             s = inspect.getsource(f)
             s = s.lstrip()
             ast = compiler.parse(s)
-            print ast
+            # print ast
             fname = f.__name__
             ast.name = _Label(fname)
             ast.sourcefile = inspect.getsourcefile(f)
diff --git a/myhdl/_toVerilog/_convert.py b/myhdl/_toVerilog/_convert.py
index 66338498..fd4141ae 100644
--- a/myhdl/_toVerilog/_convert.py
+++ b/myhdl/_toVerilog/_convert.py
@@ -244,9 +244,9 @@ class _ConvertVisitor(_ToVerilogMixin):
         self.binaryOp(node, '<<')
     def visitMod(self, node, context=None, *args):
         if context == _context.PRINT:
-            self.visit(node.left)
+            self.visit(node.left, _context.PRINT)
             self.write(", ")
-            self.visit(node.right)
+            self.visit(node.right, _context.PRINT)
         else:
             self.binaryOp(node, '%')        
     def visitMul(self, node, *args):
@@ -391,8 +391,7 @@ class _ConvertVisitor(_ToVerilogMixin):
 
     def visitConst(self, node, context=None, *args):
         if context == _context.PRINT:
-            assert type(node.value) is str
-            self.write('"Verilog %s"' % node.value)
+            self.write('"%s"' % node.value)
         else:
             self.write(node.value)
 
@@ -579,10 +578,12 @@ class _ConvertVisitor(_ToVerilogMixin):
         self.write("// pass")
 
     def handlePrint(self, node):
-        assert len(node.nodes) == 1
-        s = node.nodes[0]
         self.write('$display(')
+        s = node.nodes[0]
         self.visit(s, _context.PRINT)
+        for s in node.nodes[1:]:
+            self.write(', , ')
+            self.visit(s, _context.PRINT)
         self.write(');')
     
     def visitPrint(self, node, *args):
@@ -592,7 +593,7 @@ class _ConvertVisitor(_ToVerilogMixin):
         self.handlePrint(node)
     
     def visitRaise(self, node, *args):
-        self.write('$display("Verilog: ')
+        self.write('$display("')
         self.visit(node.expr1)
         self.write('");')
         self.writeline()
diff --git a/myhdl/test/toVerilog/test_errors.py b/myhdl/test/toVerilog/test_errors.py
index 3362d2c2..184d004b 100644
--- a/myhdl/test/toVerilog/test_errors.py
+++ b/myhdl/test/toVerilog/test_errors.py
@@ -144,6 +144,7 @@ def taskReturnVal(count, enable, clock, reset, n):
             if enable:
                 h2(cnt)
                 count.next = count + 1
+
        
 
 objfile = "inc_inst.o"
@@ -290,6 +291,8 @@ class TestErr(TestCase):
         else:
             self.fail()
 
+            
+
 
 if __name__ == '__main__':
     unittest.main()