From b9f385f65e741dae78f056e515d880384ecdc3d6 Mon Sep 17 00:00:00 2001
From: jand <none@none>
Date: Wed, 12 Nov 2003 18:55:26 +0000
Subject: [PATCH] added

---
 myhdl/_toVerilog.py                       | 24 +++++++++++------------
 myhdl/test/toVerilog/test_NotSupported.py |  4 ++--
 2 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/myhdl/_toVerilog.py b/myhdl/_toVerilog.py
index fcf14075..203cc354 100644
--- a/myhdl/_toVerilog.py
+++ b/myhdl/_toVerilog.py
@@ -36,7 +36,7 @@ from cStringIO import StringIO
 import myhdl
 from myhdl import Signal, intbv
 from myhdl._extractHierarchy import _HierExtr, _findInstanceName
-from myhdl._Error import Error
+from myhdl._Error import Error as _Error
 
 def _flatten(*args):
     l = []
@@ -44,7 +44,8 @@ def _flatten(*args):
         if type(arg) is GeneratorType:
             l.append(arg)
         elif isinstance(arg, (list, tuple)):
-            l.extend(flatten(arg))
+            for item in arg:
+                l.extend(_flatten(item))
         else:
             raise ArgumentError
     return l
@@ -52,7 +53,8 @@ def _flatten(*args):
 _converting = 0
 _profileFunc = None
 
-class ToVerilogError(Error):
+# define Error class here for clearer reporting
+class Error(_Error):
     pass
 class _error:
     pass
@@ -70,7 +72,7 @@ def toVerilog(func, *args, **kwargs):
     if _converting:
         return func(*args, **kwargs) # skip
     if not callable(func):
-        raise ArgTypeError("got %s" % type(func))
+        raise Error(_error.ArgType, "got %s" % type(func))
     _converting = 1
     try:
         outer = inspect.getouterframes(inspect.currentframe())[1]
@@ -120,12 +122,12 @@ def _analyzeSigs(hierarchy):
         for n, s in sigdict.items():
             if s._name is None:
                 if len(prefixes) > 1:
-                    s._name = '_'.join(prefixes) + '_' + n
+                    s._name = '_'.join(prefixes[1:]) + '_' + n
                 else:
                     s._name = n
                 siglist.append(s)
             if not s._nrbits:
-                raise UndefinedBitWidthError(s._name)
+                raise Error(_error.UndefinedBitWidth, s._name)
     return siglist
 
 
@@ -184,7 +186,7 @@ class _ToVerilogMixin(object):
         lineno = self.getLineNo(node)
         info = "in file %s, line %s:\n    " % \
               (self.sourcefile, self.lineoffset+lineno)
-        raise ToVerilogError(kind, msg, info)
+        raise Error(kind, msg, info)
 
     def require(self, node, test, msg=""):
         if not test:
@@ -374,6 +376,7 @@ class _AnalyzeGenVisitor(_NotSupportedVisitor, _ToVerilogMixin):
             self.visit(node.code)
             
     def visitGetattr(self, node, *args):
+        self.visit(node.expr, *args)
         assert isinstance(node.expr, ast.Name)
         assert node.expr.name in self.symdict
         obj = self.symdict[node.expr.name]
@@ -500,13 +503,11 @@ def _writeSigDecls(f, intf, siglist):
         if s._driven:
             print >> f, "reg %s%s;" % (r, s._name)
         else:
-            raise UndrivenSignalError(s._name)
+            raise Error(_error.UndrivenSignal, s._name)
     print >> f
             
 
 def _writeModuleFooter(f):
-    print >> f
-    print >> f
     print >> f, "endmodule"
     
 
@@ -600,7 +601,6 @@ class _ConvertGenVisitor(_ToVerilogMixin):
                 self.write("reg [%s-1:0] %s;" % (obj._nrbits, name))
             else:
                 raise AssertionError("unexpected type")
-        self.writeline()
                 
     def indent(self):
         self.ind += ' ' * 4
@@ -740,7 +740,6 @@ class _ConvertGenVisitor(_ToVerilogMixin):
         assert w.else_ is None
         assert isinstance(w.body.nodes[0], ast.Yield)
         sl = w.body.nodes[0].value
-        assert isinstance(sl, (ast.Tuple, ast.Name))
         self.inYield = True
         self.write("always @(")
         self.visit(sl)
@@ -757,6 +756,7 @@ class _ConvertGenVisitor(_ToVerilogMixin):
         self.writeline()
         self.write("end")
         self.writeline()
+        self.writeline()
 
     def visitGetattr(self, node):
         assert isinstance(node.expr, ast.Name)
diff --git a/myhdl/test/toVerilog/test_NotSupported.py b/myhdl/test/toVerilog/test_NotSupported.py
index d94b4567..26a36a17 100644
--- a/myhdl/test/toVerilog/test_NotSupported.py
+++ b/myhdl/test/toVerilog/test_NotSupported.py
@@ -3,14 +3,14 @@ path = os.path
 import unittest
 
 from myhdl import *
-from myhdl._toVerilog import ToVerilogError, _error
+from myhdl._toVerilog import Error, _error
 
 class TestNotSupported(unittest.TestCase):
     
     def check(self, *args):
         try:
             i = toVerilog(*args)
-        except ToVerilogError, e:
+        except Error, e:
             self.assertEqual(e.kind, _error.NotSupported)
         except:
             self.fail()