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prevent unnecesarily adding _ to signal names

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--HG--
branch : 0.9-dev
This commit is contained in:
Keerthan Jaic 2013-09-21 20:28:11 -04:00
parent 885a741889
commit bad0346b29
1 changed files with 6 additions and 4 deletions
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2
myhdl/conversion/_analyze.py
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@ -110,6 +110,7 @@ def _analyzeSigs(hierarchy, hdl='Verilog'):
if isinstance(s, _SliceSignal): if isinstance(s, _SliceSignal):
continue continue
s._name = _makeName(n, prefixes) s._name = _makeName(n, prefixes)
if '.' in n:
while s._name in sigdict: while s._name in sigdict:
s._name += '_' s._name += '_'
if not s._nrbits: if not s._nrbits:
@ -123,6 +124,7 @@ def _analyzeSigs(hierarchy, hdl='Verilog'):
if m.name is not None: if m.name is not None:
continue continue
m.name = _makeName(n, prefixes) m.name = _makeName(n, prefixes)
if '.' in n:
while m.name in memdict: while m.name in memdict:
m.name += '_' m.name += '_'
memlist.append(m) memlist.append(m)