timer benchmark

myhdl/test/benchmark/convert.py

@@ -3,6 +3,8 @@ from myhdl import *
 from test_lfsr24 import test_lfsr24
 from test_randgen import test_randgen
 from test_longdiv import test_longdiv
+from test_timer import test_timer
+from timer import timer_sig, timer_var
 
 toVerilog(test_lfsr24)
 toVHDL(test_lfsr24)
@@ -13,3 +15,5 @@ toVHDL(test_randgen)
 toVerilog(test_longdiv)
 toVHDL(test_longdiv)
 
+toVerilog(test_timer, timer_var)
+toVHDL(test_timer, timer_var)

myhdl/test/benchmark/run.sh

@@ -5,11 +5,14 @@ echo > stats.dat
 python convert.py
 
 ghdl -a pck_myhdl_07.vhd
+vlib work
+vcom pck_myhdl_07.vhd
 
 tests="
+timer
 lfsr24
-longdiv
 randgen
+longdiv
 "
 
 for test in $tests
@@ -19,37 +22,37 @@ echo ===== >> stats.dat
 
 echo python >> stats.dat
 echo ------ >> stats.dat
-#/usr/bin/time -o stats.dat -a -p python test_$test.py > $test_python.out
+/usr/bin/time -o stats.dat -a -p python test_$test.py > ${test}_python.out
 echo >> stats.dat
 
 echo pypy >> stats.dat
 echo ---- >> stats.dat
-/usr/bin/time -o stats.dat -a -p pypy test_$test.py > $test_pypy.out
+/usr/bin/time -o stats.dat -a -p pypy test_$test.py > ${test}_pypy.out
 echo >> stats.dat
 
 echo icarus >> stats.dat
 echo ------ >> stats.dat
 iverilog test_$test.v
-/usr/bin/time -o stats.dat -a -p vvp a.out test_$test > $test_icarus.out
+/usr/bin/time -o stats.dat -a -p vvp a.out test_$test > ${test}_icarus.out
 echo >> stats.dat
 
 echo ghdl >> stats.dat
 echo ---- >> stats.dat
 ghdl -a test_$test.vhd 
 ghdl -e test_$test
-/usr/bin/time -o stats.dat -a -p ghdl -r test_$test > $test_ghdl.out
+/usr/bin/time -o stats.dat -a -p ghdl -r test_$test > ${test}_ghdl.out
 echo >> stats.dat
 
 echo vlog >> stats.dat
 echo ---- >> stats.dat
 vlog test_$test.v 
-/usr/bin/time -o stats.dat -a -p vsim -c -do run.do test_$test > $test_vlog.out
+/usr/bin/time -o stats.dat -a -p vsim -c -do run.do test_$test > ${test}_vlog.out
 echo >> stats.dat
 
 echo vcom >> stats.dat
 echo ---- >> stats.dat
 vcom test_$test.vhd 
-/usr/bin/time -o stats.dat -a -p vsim -c -do run.do test_$test > $test_vcom.out
+/usr/bin/time -o stats.dat -a -p vsim -c -do run.do test_$test > ${test}_vcom.out
 echo >> stats.dat
 
 done

myhdl/test/benchmark/stats.dat

@@ -1,106 +1,47 @@
 
+Test: timer
+=====
+python
+------
+real 849.12
+user 845.32
+sys 1.96
+
+pypy
+----
+real 79.85
+user 79.49
+sys 0.18
+
+icarus
+------
+real 108.19
+user 107.79
+sys 0.18
+
+ghdl
+----
+real 145.98
+user 145.68
+sys 0.00
+
+vlog
+----
+real 258.29
+user 102.55
+sys 154.94
+
+vcom
+----
+real 216.14
+user 103.58
+sys 111.86
+
 Test: lfsr24
 =====
 python
 ------
-
-pypy
-----
-real 155.23
-user 154.79
-sys 0.07
-
-icarus
-------
-real 82.12
-user 81.90
-sys 0.01
-
-ghdl
-----
-real 63.23
-user 63.10
-sys 0.00
-
-vlog
-----
-real 262.49
-user 105.33
-sys 156.24
-
-vcom
-----
-real 236.16
-user 106.71
-sys 128.64
-
-Test: longdiv
-=====
-python
-------
-
-pypy
-----
-real 96.19
-user 95.78
-sys 0.16
-
-icarus
-------
-real 48.61
-user 48.48
-sys 0.02
-
-ghdl
-----
-real 43.79
-user 43.68
-sys 0.01
-
-vlog
-----
-real 54.01
-user 21.91
-sys 31.74
-
-vcom
-----
-real 54.12
-user 26.39
-sys 27.33
-
-Test: randgen
-=====
-python
-------
-
-pypy
-----
-real 261.68
-user 260.78
-sys 0.23
-
-icarus
-------
-real 170.46
-user 169.92
-sys 0.14
-
-ghdl
-----
-real 10.40
-user 8.14
-sys 2.22
-
-vlog
-----
-real 82.51
-user 37.88
-sys 42.87
-
-vcom
-----
-real 56.55
-user 27.88
-sys 26.97
-
+Command exited with non-zero status 1
+real 1564.51
+user 1557.88
+sys 3.20

myhdl/test/benchmark/test_longdiv.py

@@ -58,7 +58,7 @@ def test_longdiv():
         reset.next = 0
         start.next = 0
         yield clock.negedge
-        for i in range(2**17):
+        for i in range(2**18):
             yield clock.negedge
             enable.next = 1
             yield clock.negedge

myhdl/test/benchmark/test_timer.py

@@ -0,0 +1,48 @@
+from myhdl import *
+
+from timer import timer_sig, timer_var
+
+def test_timer(timer):
+
+    MAXVAL = 1234
+
+    clock = Signal(bool())
+    reset = Signal(bool())
+    flag = Signal(bool())
+
+    dut = timer(flag, clock, reset, MAXVAL)
+
+    @instance
+    def clkgen():
+        clock.next = 0
+        reset.next = 0
+        yield delay(10)
+        reset.next = 1
+        yield delay(10)
+        reset.next = 0
+        yield delay(10)
+        for i in range(2**26):
+            clock.next = not clock
+            yield delay(10)
+
+    @instance
+    def monitor():
+        count = intbv(0, min=0, max=MAXVAL+1)
+        seen = False
+        while True:
+            yield clock.posedge
+            if seen:
+                if flag:
+                    assert count == MAXVAL
+                else:
+                    count += 1
+            if flag:
+                seen = True
+                count[:] = 0
+
+    return dut, clkgen, monitor
+
+if __name__ == '__main__':
+    sim = Simulation(test_timer(timer_var))
+    sim.run()
+	

myhdl/test/benchmark/testrun.sh

@@ -1,48 +1,58 @@
 #!/bin/bash
 
-echo > stats.out
+echo > stats.dat
+
+python convert.py
 
 ghdl -a pck_myhdl_07.vhd
+vlib work
+vcom pck_myhdl_07.vhd
 
-self_tests="
-divider
+tests="
+timer
 "
 
-for test in $self_tests
+for test in $tests
 do
-echo Test: $test >> stats.out
-echo ===== >> stats.out
+echo Test: $test >> stats.dat
+echo ===== >> stats.dat
 
+echo python >> stats.dat
+echo ------ >> stats.dat
+#/usr/bin/time -o stats.dat -a -p python test_$test.py > ${test}_python.out
+echo >> stats.dat
 
-echo pypy >> stats.out
-echo ---- >> stats.out
-/usr/bin/time -o stats.out -a -p pypy test_$test.py
-echo >> stat.out
+echo pypy >> stats.dat
+echo ---- >> stats.dat
+/usr/bin/time -o stats.dat -a -p pypy test_$test.py > ${test}_pypy.out
+echo >> stats.dat
 
-echo icarus >> stats.out
-echo ------ >> stats.out
+echo icarus >> stats.dat
+echo ------ >> stats.dat
 iverilog test_$test.v
-/usr/bin/time -o stats.out -a -p vvp a.out test_$test
-echo >> stat.out
+/usr/bin/time -o stats.dat -a -p vvp a.out test_$test > ${test}_icarus.out
+echo >> stats.dat
 
-echo ghdl >> stats.out
-echo ---- >> stats.out
+echo ghdl >> stats.dat
+echo ---- >> stats.dat
 ghdl -a test_$test.vhd 
 ghdl -e test_$test
-/usr/bin/time -o stats.out -a -p ghdl -r test_$test
-echo >> stats.out
+/usr/bin/time -o stats.dat -a -p ghdl -r test_$test > ${test}_ghdl.out
+echo >> stats.dat
 
-echo vlog >> stats.out
-echo ---- >> stats.out
+echo vlog >> stats.dat
+echo ---- >> stats.dat
 vlog test_$test.v 
-/usr/bin/time -o stats.out -a -p vsim -c -do run.do test_$test
-echo >> stats.out
+/usr/bin/time -o stats.dat -a -p vsim -c -do run.do test_$test > ${test}_vlog.out
+echo >> stats.dat
 
-echo vcom >> stats.out
-echo ---- >> stats.out
+echo vcom >> stats.dat
+echo ---- >> stats.dat
 vcom test_$test.vhd 
-/usr/bin/time -o stats.out -a -p vsim -c -do run.do test_$test
-echo >> stats.out
+/usr/bin/time -o stats.dat -a -p vsim -c -do run.do test_$test > ${test}_vcom.out
+echo >> stats.dat
 
 done
 
+
+

myhdl/test/benchmark/timer.py

@@ -0,0 +1,41 @@
+from myhdl import *
+
+def timer_sig(flag, clock, reset, MAXVAL):
+
+    count = Signal(intbv(0, min=0, max=MAXVAL+1))
+
+    @always (clock.posedge, reset.posedge)
+    def logic():
+        if reset == 1:
+            count.next = 0
+        else:
+            flag.next = 0
+            if count == MAXVAL:
+                flag.next = 1
+                count.next = 0
+            else:
+                count.next = count + 1
+
+    return logic
+
+
+def timer_var(flag, clock, reset, MAXVAL):
+
+    @instance
+    def logic():
+        count = intbv(0, min=0, max=MAXVAL+1)
+        while True:
+            yield clock.posedge, reset.posedge
+            if reset == 1:
+                count[:] = 0
+            else:
+                flag.next = 0
+                if count == MAXVAL:
+                    flag.next = 1
+                    count[:] = 0
+                else:
+                    count += 1
+
+    return logic
+
+