Migrate some tests

myhdl/_Simulation.py

@@ -109,10 +109,6 @@ class Simulation(object):
     def quit(self):
         self._finalize()
 
-    def runc(self, duration=0, quiet=0):
-        simrunc.run(sim=self, duration=duration, quiet=quiet)
-
-
     def run(self, duration=None, quiet=0):
 
         """ Run the simulation for some duration.

myhdl/test/conversion/toVerilog/test_bugreports.py

@@ -11,6 +11,7 @@ from .util import verilogCompile
 
 width = 8
 
+
 def add(x,a,b) :
     def logic() :
         x.next = a + b
@@ -91,6 +92,7 @@ test()
 
 from .test_fsm import FramerCtrl
 
+@block
 def mid(SOF, clk, reset_n):
     t_State = enum('SEARCH', 'CONFIRM', 'SYNC')
     syncFlag = Signal(bool(0))
@@ -101,6 +103,7 @@ def mid(SOF, clk, reset_n):
     return fsm_1
 
 
+@block
 def top(SOF, clk, reset_n):
     mid_1 = mid(SOF, clk, reset_n)
     return mid_1
@@ -111,7 +114,7 @@ def test():
     reset_n = Signal(bool(1))
     SOF = Signal(bool(0))
    
-    toVerilog(top, SOF, clk, reset_n)
+    top(SOF, clk, reset_n).convert()
     verilogCompile(top.__name__)
 
 test()

myhdl/test/conversion/toVerilog/test_fsm.py

@@ -16,8 +16,9 @@ t_State_b = enum('SEARCH', 'CONFIRM', 'SYNC')
 t_State_oh = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot")
 t_State_oc = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_cold")
 
+@block
 def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State):
-    
+
     """ Framing control FSM.
 
     SOF -- start-of-frame output bit
@@ -25,9 +26,9 @@ def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State):
     syncFlag -- sync pattern found indication input
     clk -- clock input
     reset_n -- active low reset
-    
+
     """
-    
+
     index = Signal(intbv(0)[8:]) # position in frame
 
     @always(clk.posedge, reset_n.negedge)
@@ -56,12 +57,12 @@ def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State):
                 SOF.next = (index == FRAME_SIZE-1)
             else:
                 raise ValueError("Undefined state")
-            
+
     return FSM
 
-
+@block
 def FramerCtrl_alt(SOF, state, syncFlag, clk, reset_n, t_State):
-    
+
     """ Framing control FSM.
 
     SOF -- start-of-frame output bit
@@ -69,9 +70,9 @@ def FramerCtrl_alt(SOF, state, syncFlag, clk, reset_n, t_State):
     syncFlag -- sync pattern found indication input
     clk -- clock input
     reset_n -- active low reset
-    
+
     """
-    
+
 
     @instance
     def FSM():
@@ -109,9 +110,9 @@ def FramerCtrl_alt(SOF, state, syncFlag, clk, reset_n, t_State):
 
     return FSM
 
-
+@block
 def FramerCtrl_ref(SOF, state, syncFlag, clk, reset_n, t_State):
-    
+
     """ Framing control FSM.
 
     SOF -- start-of-frame output bit
@@ -119,9 +120,9 @@ def FramerCtrl_ref(SOF, state, syncFlag, clk, reset_n, t_State):
     syncFlag -- sync pattern found indication input
     clk -- clock input
     reset_n -- active low reset
-    
+
     """
-    
+
     @instance
     def logic():
         index = intbv(0, min=0, max=8) # position in frame
@@ -155,14 +156,14 @@ def FramerCtrl_ref(SOF, state, syncFlag, clk, reset_n, t_State):
     return logic
 
 
-
-
+@block
 def FramerCtrl_v(name, SOF, state, syncFlag, clk, reset_n):
     return setupCosimulation(**locals())
-    
+
 
 class FramerCtrlTest(TestCase):
-    
+
+    @block
     def bench(self, FramerCtrl, t_State):
 
         SOF = Signal(bool(0))
@@ -174,10 +175,11 @@ class FramerCtrlTest(TestCase):
         state_v = Signal(intbv(0)[8:])
 
         framerctrl_ref_inst = FramerCtrl_ref(SOF, state, syncFlag, clk, reset_n, t_State)
-        framerctrl_inst = toVerilog(FramerCtrl, SOF, state, syncFlag, clk, reset_n, t_State)
+        framerctrl_inst = FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State).convert()
         framerctrl_v_inst = FramerCtrl_v(FramerCtrl.__name__,
                                          SOF_v, state_v, syncFlag, clk, reset_n)
 
+        @instance
         def clkgen():
             reset_n.next = 1
             yield delay(10)
@@ -189,6 +191,7 @@ class FramerCtrlTest(TestCase):
                 yield delay(10)
                 clk.next = not clk
 
+        @instance
         def stimulus():
             for i in range(3):
                 yield clk.posedge
@@ -200,6 +203,7 @@ class FramerCtrlTest(TestCase):
                     yield clk.posedge
             raise StopSimulation
 
+        @instance
         def check():
             while 1:
                 yield clk.negedge
@@ -208,25 +212,23 @@ class FramerCtrlTest(TestCase):
                 # print "MyHDL: %s %s" % (SOF, hex(state))
                 # print "Verilog: %s %s" % (SOF_v, hex(state_v))
 
-        return framerctrl_ref_inst, framerctrl_v_inst, clkgen(), stimulus(), check()
-    
+        return framerctrl_ref_inst, framerctrl_v_inst, clkgen, stimulus, check
+
 
     def testRef(self):
         for t_State in (t_State_b, t_State_oc, t_State_oh):
             tb_fsm = self.bench(FramerCtrl_ref, t_State)
-            sim = Simulation(tb_fsm)
-            sim.run()
-        
+            tb_fsm.run()
+
     def testAlt(self):
         for t_State in (t_State_b, t_State_oc, t_State_oh):
             tb_fsm = self.bench(FramerCtrl_alt, t_State)
-            sim = Simulation(tb_fsm)
-            sim.run()
-            
+            tb_fsm.run()
+
     def testDoc(self):
         tb_fsm = self.bench(FramerCtrl, t_State_oh)
-        sim = Simulation(tb_fsm)
-        sim.run()
+        tb_fsm.run()
+
 
 if __name__ == '__main__':
     unittest.main()