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Migrate some tests

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This commit is contained in:
Jan Decaluwe 2016-03-15 16:21:43 +01:00
parent b0e0928ab4
commit bbac626db4
3 changed files with 33 additions and 32 deletions
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4
myhdl/_Simulation.py
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@ -109,10 +109,6 @@ class Simulation(object):
def quit(self): def quit(self):
self._finalize() self._finalize()
def runc(self, duration=0, quiet=0):
simrunc.run(sim=self, duration=duration, quiet=quiet)
def run(self, duration=None, quiet=0): def run(self, duration=None, quiet=0):
""" Run the simulation for some duration. """ Run the simulation for some duration.

5
myhdl/test/conversion/toVerilog/test_bugreports.py
View File

@ -11,6 +11,7 @@ from .util import verilogCompile
width = 8 width = 8
def add(x,a,b) : def add(x,a,b) :
def logic() : def logic() :
x.next = a + b x.next = a + b
@ -91,6 +92,7 @@ test()
from .test_fsm import FramerCtrl from .test_fsm import FramerCtrl
@block
def mid(SOF, clk, reset_n): def mid(SOF, clk, reset_n):
t_State = enum('SEARCH', 'CONFIRM', 'SYNC') t_State = enum('SEARCH', 'CONFIRM', 'SYNC')
syncFlag = Signal(bool(0)) syncFlag = Signal(bool(0))
@ -101,6 +103,7 @@ def mid(SOF, clk, reset_n):
return fsm_1 return fsm_1
@block
def top(SOF, clk, reset_n): def top(SOF, clk, reset_n):
mid_1 = mid(SOF, clk, reset_n) mid_1 = mid(SOF, clk, reset_n)
return mid_1 return mid_1
@ -111,7 +114,7 @@ def test():
reset_n = Signal(bool(1)) reset_n = Signal(bool(1))
SOF = Signal(bool(0)) SOF = Signal(bool(0))
toVerilog(top, SOF, clk, reset_n) top(SOF, clk, reset_n).convert()
verilogCompile(top.__name__) verilogCompile(top.__name__)
test() test()

26
myhdl/test/conversion/toVerilog/test_fsm.py
View File

@ -16,6 +16,7 @@ t_State_b = enum('SEARCH', 'CONFIRM', 'SYNC')
t_State_oh = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot") t_State_oh = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot")
t_State_oc = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_cold") t_State_oc = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_cold")
@block
def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State): def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State):
""" Framing control FSM. """ Framing control FSM.
@ -59,7 +60,7 @@ def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State):
return FSM return FSM
@block
def FramerCtrl_alt(SOF, state, syncFlag, clk, reset_n, t_State): def FramerCtrl_alt(SOF, state, syncFlag, clk, reset_n, t_State):
""" Framing control FSM. """ Framing control FSM.
@ -109,7 +110,7 @@ def FramerCtrl_alt(SOF, state, syncFlag, clk, reset_n, t_State):
return FSM return FSM
@block
def FramerCtrl_ref(SOF, state, syncFlag, clk, reset_n, t_State): def FramerCtrl_ref(SOF, state, syncFlag, clk, reset_n, t_State):
""" Framing control FSM. """ Framing control FSM.
@ -155,14 +156,14 @@ def FramerCtrl_ref(SOF, state, syncFlag, clk, reset_n, t_State):
return logic return logic
@block
def FramerCtrl_v(name, SOF, state, syncFlag, clk, reset_n): def FramerCtrl_v(name, SOF, state, syncFlag, clk, reset_n):
return setupCosimulation(**locals()) return setupCosimulation(**locals())
class FramerCtrlTest(TestCase): class FramerCtrlTest(TestCase):
@block
def bench(self, FramerCtrl, t_State): def bench(self, FramerCtrl, t_State):
SOF = Signal(bool(0)) SOF = Signal(bool(0))
@ -174,10 +175,11 @@ class FramerCtrlTest(TestCase):
state_v = Signal(intbv(0)[8:]) state_v = Signal(intbv(0)[8:])
framerctrl_ref_inst = FramerCtrl_ref(SOF, state, syncFlag, clk, reset_n, t_State) framerctrl_ref_inst = FramerCtrl_ref(SOF, state, syncFlag, clk, reset_n, t_State)
framerctrl_inst = toVerilog(FramerCtrl, SOF, state, syncFlag, clk, reset_n, t_State) framerctrl_inst = FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State).convert()
framerctrl_v_inst = FramerCtrl_v(FramerCtrl.__name__, framerctrl_v_inst = FramerCtrl_v(FramerCtrl.__name__,
SOF_v, state_v, syncFlag, clk, reset_n) SOF_v, state_v, syncFlag, clk, reset_n)
@instance
def clkgen(): def clkgen():
reset_n.next = 1 reset_n.next = 1
yield delay(10) yield delay(10)
@ -189,6 +191,7 @@ class FramerCtrlTest(TestCase):
yield delay(10) yield delay(10)
clk.next = not clk clk.next = not clk
@instance
def stimulus(): def stimulus():
for i in range(3): for i in range(3):
yield clk.posedge yield clk.posedge
@ -200,6 +203,7 @@ class FramerCtrlTest(TestCase):
yield clk.posedge yield clk.posedge
raise StopSimulation raise StopSimulation
@instance
def check(): def check():
while 1: while 1:
yield clk.negedge yield clk.negedge
@ -208,25 +212,23 @@ class FramerCtrlTest(TestCase):
# print "MyHDL: %s %s" % (SOF, hex(state)) # print "MyHDL: %s %s" % (SOF, hex(state))
# print "Verilog: %s %s" % (SOF_v, hex(state_v)) # print "Verilog: %s %s" % (SOF_v, hex(state_v))
return framerctrl_ref_inst, framerctrl_v_inst, clkgen(), stimulus(), check() return framerctrl_ref_inst, framerctrl_v_inst, clkgen, stimulus, check
def testRef(self): def testRef(self):
for t_State in (t_State_b, t_State_oc, t_State_oh): for t_State in (t_State_b, t_State_oc, t_State_oh):
tb_fsm = self.bench(FramerCtrl_ref, t_State) tb_fsm = self.bench(FramerCtrl_ref, t_State)
sim = Simulation(tb_fsm) tb_fsm.run()
sim.run()
def testAlt(self): def testAlt(self):
for t_State in (t_State_b, t_State_oc, t_State_oh): for t_State in (t_State_b, t_State_oc, t_State_oh):
tb_fsm = self.bench(FramerCtrl_alt, t_State) tb_fsm = self.bench(FramerCtrl_alt, t_State)
sim = Simulation(tb_fsm) tb_fsm.run()
sim.run()
def testDoc(self): def testDoc(self):
tb_fsm = self.bench(FramerCtrl, t_State_oh) tb_fsm = self.bench(FramerCtrl, t_State_oh)
sim = Simulation(tb_fsm) tb_fsm.run()
sim.run()
if __name__ == '__main__': if __name__ == '__main__':
unittest.main() unittest.main()