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Merge pull request #130 from jck/py35

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Python 3 fixes, test improvements
This commit is contained in:
jandecaluwe 2015-10-07 20:23:12 +02:00
commit bd0cfba9a7
50 changed files with 174 additions and 139 deletions
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5
.travis.yml
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@ -7,6 +7,7 @@ python:
- "2.7"
- "pypy"
- "3.4"
- "3.5"
addons:
apt:
@ -30,6 +31,10 @@ matrix:
env: CI_TARGET=iverilog
- python: "3.4"
env: CI_TARGET=ghdl
- python: "3.5"
env: CI_TARGET=iverilog
- python: "3.5"
env: CI_TARGET=ghdl
script: ./scripts/ci.sh

3
myhdl/_enum.py
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@ -85,6 +85,9 @@ def enum(*names, **kwargs):
__str__ = __repr__
def __int__(self):
return int(self._val, 2)
def __hex__(self):
return hex(int(self._val, 2))

20
myhdl/conversion/_analyze.py
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@ -244,6 +244,12 @@ class _FirstPassVisitor(ast.NodeVisitor, _ConversionMixin):
self.raiseError(node, _error.NotSupported, "list")
def visitSliceObj(self, node):
self.raiseError(node, _error.NotSupported, "slice object")
# All try blocks from python 3.3+
def visit_Try(self, node):
self.raiseError(node, _error.NotSupported, "try statement")
# Legacy try blocks
def visit_TryExcept(self, node):
self.raiseError(node, _error.NotSupported, "try-except statement")
def visit_TryFinally(self, node):
@ -257,11 +263,19 @@ class _FirstPassVisitor(ast.NodeVisitor, _ConversionMixin):
self.visit(node.value)
def visit_Call(self, node):
if node.starargs:
# ast.Call signature changed in python 3.5
# http://greentreesnakes.readthedocs.org/en/latest/nodes.html#Call
if sys.version_info >= (3, 5):
starargs = any(isinstance(arg, ast.Starred) for arg in node.args)
kwargs = any(kw.arg is None for kw in node.keywords)
else:
starargs = node.starargs is not None
kwargs = node.kwargs is not None
if starargs:
self.raiseError(node, _error.NotSupported, "extra positional arguments")
if node.kwargs:
if kwargs:
self.raiseError(node, _error.NotSupported, "extra named arguments")
# f = eval(_unparse(node.node), self.tree.symdict)
self.generic_visit(node)
def visit_Compare(self, node):

1
myhdl/test/__init__.py
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@ -1 +0,0 @@

0
myhdl/test/bugs/__init__.py Normal file
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5
myhdl/test/conftest.py
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@ -1,3 +1,5 @@
import sys
import py
import pytest
@ -8,6 +10,9 @@ xfail = pytest.mark.xfail
all_sims = list(_simulators)
if sys.version_info[0] > 2:
collect_ignore = ['conversion/toVerilog/test_not_supported_py2.py']
def pytest_addoption(parser):
parser.addoption("--sim", action="store", choices=all_sims,
help="HDL Simulator")

0
myhdl/test/conversion/general/__init__.py Normal file
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0
myhdl/test/conversion/toVHDL/__init__.py Normal file
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4
myhdl/test/conversion/toVHDL/test_custom.py
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@ -215,7 +215,7 @@ def check(count, enable, clock, reset, n):
expect = 0
yield reset.posedge
# assert count == expect
print count
print(count)
while 1:
yield clock.posedge
if enable:
@ -223,7 +223,7 @@ def check(count, enable, clock, reset, n):
yield delay(1)
# print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v)
# assert count == expect
print count
print(count)
return logic

10
myhdl/test/conversion/toVHDL/test_enum.py
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@ -40,23 +40,23 @@ def bench_enum():
a.next = 0xaa
b.next = 0x55
yield clock.posedge
print 'a=%s b=%s' % (a, b)
print('a=%s b=%s' % (a, b))
op.next = bitwise_op.BW_AND
yield clock.posedge
print c
print(c)
op.next = bitwise_op.BW_ANDN
yield clock.posedge
print c
print(c)
op.next = bitwise_op.BW_OR
yield clock.posedge
print c
print(c)
op.next = bitwise_op.BW_XOR
yield clock.posedge
print c
print(c)
raise StopSimulation

2
myhdl/test/conversion/toVHDL/test_loops.py
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@ -34,7 +34,7 @@ def LoopBench(LoopTest):
for i in range(100):
a.next = data[i]
yield delay(10)
print z
print(z)
return stimulus, looptest_inst

4
myhdl/test/conversion/toVHDL/test_newcustom.py
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@ -215,7 +215,7 @@ def check(count, enable, clock, reset, n):
expect = 0
yield reset.posedge
# assert count == expect
print count
print(count)
while 1:
yield clock.posedge
if enable:
@ -223,7 +223,7 @@ def check(count, enable, clock, reset, n):
yield delay(1)
# print "%d count %s expect %s count_v %s" % (now(), count, expect, count_v)
# assert count == expect
print count
print(count)
return logic

70
myhdl/test/conversion/toVHDL/test_ops.py
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@ -145,27 +145,27 @@ def binaryBench(m, n):
yield left, right
yield delay(1)
print Bitand
print Bitor
print Bitxor
print FloorDiv
print LeftShift
print(Bitand)
print(Bitor)
print(Bitxor)
print(FloorDiv)
print(LeftShift)
# print Pow, Pow_v
print Modulo
print RightShift
print Mul
print Sub
print Sum
print int(EQ)
print int(NE)
print int(LT)
print int(GT)
print int(LE)
print int(GE)
print int(Booland)
print int(Boolor)
print(Modulo)
print(RightShift)
print(Mul)
print(Sub)
print(Sum)
print(int(EQ))
print(int(NE))
print(int(LT))
print(int(GT))
print(int(LE))
print(int(GE))
print(int(Booland))
print(int(Boolor))
return binops, stimulus, check
@ -253,11 +253,11 @@ def multiBench(m, n, p):
yield argm, argn, argp
yield delay(1)
print Bitand
print Bitor
print Bitxor
print int(Booland)
print int(Boolor)
print(Bitand)
print(Bitor)
print(Bitxor)
print(int(Booland))
print(int(Boolor))
return multiops, stimulus, check
@ -315,8 +315,8 @@ def unaryBench(m):
while 1:
yield arg
yield delay(1)
print int(Not_kw)
print Invert
print(int(Not_kw))
print(Invert)
# check unary operator support in vhdl
# print UnaryAdd
# print UnarySub
@ -449,16 +449,16 @@ def augmBench(m, n):
while True:
yield left, right
yield delay(1)
print Bitand
print Bitor
print Bitxor
print Sub
print Sum
print FloorDiv
print LeftShift
print Modulo
print Mul
print RightShift
print(Bitand)
print(Bitor)
print(Bitxor)
print(Sub)
print(Sum)
print(FloorDiv)
print(LeftShift)
print(Modulo)
print(Mul)
print(RightShift)
return augmops, stimulus, check

50
myhdl/test/conversion/toVHDL/test_signed.py
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@ -163,24 +163,24 @@ def binaryBench(Ll, Ml, Lr, Mr):
## self.assertEqual(Bitor, Bitor_v)
## self.assertEqual(Bitxor, Bitxor_v)
## ## self.assertEqual(FloorDiv, FloorDiv_v)
print LeftShift
print(LeftShift)
# print Modulo
print Mul
print(Mul)
# self.assertEqual(Pow, Pow_v)
print RightShift
print Sub
print Sum
print Sum1
print Sum2
print Sum3
print int(EQ)
print int(NE)
print int(LT)
print int(GT)
print int(LE)
print int(GE)
print int(BoolAnd)
print int(BoolOr)
print(RightShift)
print(Sub)
print(Sum)
print(Sum1)
print(Sum2)
print(Sum3)
print(int(EQ))
print(int(NE))
print(int(LT))
print(int(GT))
print(int(LE))
print(int(GE))
print(int(BoolAnd))
print(int(BoolOr))
return binops, stimulus, check
@ -255,9 +255,9 @@ def unaryBench( m):
yield arg
yield delay(1)
# print BoolNot
print Invert
print(Invert)
# print UnaryAdd
print UnarySub
print(UnarySub)
return unaryops, stimulus, check
@ -399,12 +399,12 @@ def augmBench( Ll, Ml, Lr, Mr):
## self.assertEqual(Bitor, Bitor_v)
## self.assertEqual(Bitxor, Bitxor_v)
## self.assertEqual(FloorDiv, FloorDiv_v)
print LeftShift
print(LeftShift)
## self.assertEqual(Modulo, Modulo_v)
print Mul
print RightShift
print Sub
print Sum
print(Mul)
print(RightShift)
print(Sub)
print(Sum)
return augmops, stimulus, check
@ -488,8 +488,8 @@ def expressionsBench():
while 1:
yield clk.posedge
yield delay(1)
print int(a)
print int(b)
print(int(a))
print(int(b))
@instance
def clkgen():

0
myhdl/test/conversion/toVerilog/__init__.py Normal file
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6
myhdl/test/conversion/toVerilog/test_GrayInc.py
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@ -6,10 +6,10 @@ from random import randrange
from myhdl import *
from test_bin2gray import bin2gray
from test_inc import inc
from .test_bin2gray import bin2gray
from .test_inc import inc
from util import setupCosimulation
from .util import setupCosimulation
ACTIVE_LOW, INACTIVE_HIGH = 0, 1

27
myhdl/test/conversion/toVerilog/test_NotSupported.py
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@ -48,20 +48,6 @@ class TestNotSupported(unittest.TestCase):
return logic
self.check(g, z, a)
def testBackquote(self):
a = Signal(bool())
z = Signal(bool())
def g(z, a):
@instance
def logic():
while 1:
yield a
z.next = 1
`a`
return logic
self.check(g, z, a)
def testClass(self):
a = Signal(bool())
z = Signal(bool())
@ -102,19 +88,6 @@ class TestNotSupported(unittest.TestCase):
return logic
self.check(g, z, a)
def testExec(self):
a = Signal(bool())
z = Signal(bool())
def g(z, a):
@instance
def logic():
while 1:
yield a
z.next = 1
exec "1 + 2" in globals , locals
return logic
self.check(g, z, a)
def testFrom(self):
a = Signal(bool())
z = Signal(bool())

4
myhdl/test/conversion/toVerilog/test_RandomScrambler.py
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@ -10,7 +10,7 @@ import time
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
N = 8
M = 2 ** N
@ -25,7 +25,7 @@ def XorGate(z, a, b, c):
return logic
def randOthers(i, n):
l = range(n)
l = list(range(n))
l.remove(i)
random.shuffle(l)
return l[0], l[1]

2
myhdl/test/conversion/toVerilog/test_always_comb.py
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@ -32,7 +32,7 @@ from unittest import TestCase
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
QUIET = 1

2
myhdl/test/conversion/toVerilog/test_beh.py
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@ -9,7 +9,7 @@ random.seed(2)
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
ACTIVE_LOW, INACTIVE_HIGH = 0, 1

2
myhdl/test/conversion/toVerilog/test_bin2gray.py
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@ -6,7 +6,7 @@ from unittest import TestCase
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
def bin2gray2(B, G, width):
""" Gray encoder.

4
myhdl/test/conversion/toVerilog/test_bugreports.py
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@ -1,7 +1,7 @@
from __future__ import absolute_import
from myhdl import *
from util import verilogCompile
from .util import verilogCompile
#############################
# bug report (Tom Dillon)
@ -88,7 +88,7 @@ test()
# case variable name in embedded FSM
####################################
from test_fsm import FramerCtrl
from .test_fsm import FramerCtrl
def mid(SOF, clk, reset_n):
t_State = enum('SEARCH', 'CONFIRM', 'SYNC')

2
myhdl/test/conversion/toVerilog/test_custom.py
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@ -9,7 +9,7 @@ random.seed(2)
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
from myhdl import ConversionError
from myhdl.conversion._misc import _error

2
myhdl/test/conversion/toVerilog/test_dec.py
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@ -9,7 +9,7 @@ random.seed(2)
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
ACTIVE_LOW, INACTIVE_HIGH = 0, 1

2
myhdl/test/conversion/toVerilog/test_edge.py
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@ -9,7 +9,7 @@ random.seed(2)
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
ACTIVE_LOW, INACTIVE_HIGH = 0, 1

2
myhdl/test/conversion/toVerilog/test_fsm.py
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@ -6,7 +6,7 @@ from unittest import TestCase
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
# SEARCH, CONFIRM, SYNC = range(3)
ACTIVE_LOW = 0

8
myhdl/test/conversion/toVerilog/test_hec.py
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@ -6,7 +6,7 @@ from random import randrange
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
COSET = 0x55
@ -128,9 +128,9 @@ def HecCalculator_v(name, hec, header):
headers = [ 0x00000000L,
0x01234567L,
0xbac6f4caL
headers = [ 0x00000000,
0x01234567,
0xbac6f4ca
]
headers.extend([randrange(2**32-1) for i in range(10)])

2
myhdl/test/conversion/toVerilog/test_inc.py
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@ -9,7 +9,7 @@ random.seed(2)
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
ACTIVE_LOW, INACTIVE_HIGH = 0, 1

2
myhdl/test/conversion/toVerilog/test_inc_initial.py
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@ -9,7 +9,7 @@ random.seed(2)
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
ACTIVE_LOW, INACTIVE_HIGH = 0, 1

2
myhdl/test/conversion/toVerilog/test_infer.py
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@ -8,7 +8,7 @@ from myhdl import *
from myhdl import ConversionError
from myhdl.conversion._misc import _error
from util import setupCosimulation
from .util import setupCosimulation
b = c = 2

2
myhdl/test/conversion/toVerilog/test_loops.py
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@ -7,7 +7,7 @@ from random import randrange
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
def ForLoop1(a, out):
@instance

2
myhdl/test/conversion/toVerilog/test_misc.py
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@ -6,7 +6,7 @@ from random import randrange
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
### test of constant wire support ###

2
myhdl/test/conversion/toVerilog/test_newcustom.py
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@ -9,7 +9,7 @@ random.seed(2)
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
from myhdl import ConversionError
from myhdl.conversion._misc import _error

34
myhdl/test/conversion/toVerilog/test_not_supported_py2.py Normal file
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@ -0,0 +1,34 @@
import pytest
from myhdl import instance, Signal, toVerilog, ConversionError
from myhdl.conversion._misc import _error
from helpers import raises_kind
def check(*args):
with raises_kind(ConversionError, _error.NotSupported):
toVerilog(*args)
def test_Backquote():
a = Signal(bool())
z = Signal(bool())
def g(z, a):
@instance
def logic():
while 1:
yield a
z.next = 1
`a`
return logic
check(g, z, a)
def testExec():
a = Signal(bool())
z = Signal(bool())
def g(z, a):
@instance
def logic():
while 1:
yield a
z.next = 1
exec "1 + 2" in globals , locals
return logic
check(g, z, a)

2
myhdl/test/conversion/toVerilog/test_ops.py
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@ -9,7 +9,7 @@ random.seed(2)
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
def binaryOps(

2
myhdl/test/conversion/toVerilog/test_ram.py
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@ -6,7 +6,7 @@ from unittest import TestCase
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
def ram(dout, din, addr, we, clk, depth=128):
""" Simple ram model """

2
myhdl/test/conversion/toVerilog/test_rom.py
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@ -7,7 +7,7 @@ from random import randrange
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
D = 256

2
myhdl/test/conversion/toVerilog/test_signed.py
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@ -9,7 +9,7 @@ random.seed(2)
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
def binaryOps(

2
myhdl/test/conversion/toVerilog/test_tristate.py
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@ -3,7 +3,7 @@ path = os.path
import unittest
from myhdl import *
from util import setupCosimulation
from .util import setupCosimulation
def tristate_obuf(A, Y, OE):
'''three-state output buffer'''

0
myhdl/test/conversion/toVerilog2/__init__.py Normal file
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2
myhdl/test/conversion/toVerilog2/test_loops.py
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@ -33,7 +33,7 @@ def LoopBench(LoopTest):
for i in range(100):
a.next = data[i]
yield delay(10)
print z
print(z)
return stimulus, looptest_inst

0
myhdl/test/core/__init__.py Normal file
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4
myhdl/test/core/test_Cosimulation.py
View File

@ -28,7 +28,9 @@ import sys
from myhdl import Signal
from myhdl._compat import to_bytes
from myhdl._Cosimulation import Cosimulation, CosimulationError, _error
from utils import raises_kind
if __name__ != '__main__':
from helpers import raises_kind
random.seed(1) # random, but deterministic

2
myhdl/test/core/test_Simulation.py
View File

@ -27,7 +27,7 @@ from unittest import TestCase
from myhdl import (Signal, Simulation, SimulationError, StopSimulation, delay,
intbv, join, now)
from myhdl._Simulation import _error
from utils import raises_kind
from helpers import raises_kind
random.seed(1) # random, but deterministic

2
myhdl/test/core/test_always.py
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@ -27,7 +27,7 @@ from myhdl import (AlwaysError, Signal, Simulation, StopSimulation, delay,
from myhdl._always import _error, always
from myhdl._Waiter import (_DelayWaiter, _EdgeTupleWaiter, _EdgeWaiter,
_SignalTupleWaiter, _SignalWaiter, _Waiter)
from utils import raises_kind
from helpers import raises_kind
# random.seed(3) # random, but deterministic

2
myhdl/test/core/test_always_comb.py
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@ -27,7 +27,7 @@ from myhdl import (AlwaysCombError, Signal, Simulation, StopSimulation, delay,
instances, intbv, now)
from myhdl._always_comb import _error, always_comb
from myhdl._Waiter import _SignalTupleWaiter, _SignalWaiter, _Waiter
from utils import raises_kind
from helpers import raises_kind
# random.seed(3) # random, but deterministic

2
myhdl/test/core/test_always_seq.py
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@ -1,7 +1,7 @@
from myhdl import *
from myhdl import Signal
from myhdl._always_seq import AlwaysSeqError, _error, always_seq
from utils import raises_kind
from helpers import raises_kind
def test_clock():

2
myhdl/test/core/test_instance.py
View File

@ -23,7 +23,7 @@ from __future__ import absolute_import
from myhdl import (InstanceError, Signal, Simulation, StopSimulation, delay,
instances, intbv, now)
from myhdl._instance import _error, instance
from utils import raises_kind
from helpers import raises_kind
# random.seed(3) # random, but deterministic

2
myhdl/test/core/test_traceSignals.py
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@ -27,7 +27,7 @@ import pytest
from myhdl import Signal, Simulation, _simulator, delay, instance, intbv
from myhdl._traceSignals import TraceSignalsError, _error, traceSignals
from utils import raises_kind
from helpers import raises_kind
random.seed(1) # random, but deterministic
path = os.path

2
myhdl/test/core/utils.py → myhdl/test/helpers.py
View File

@ -8,7 +8,7 @@ class raises_kind(object):
def __enter__(self):
return None
def __exit__(self, *tp):
__tracebackhide__ = True
if tp[0] is None: