diff --git a/myhdl/_always_seq.py b/myhdl/_always_seq.py
index 023b6548..71b74542 100644
--- a/myhdl/_always_seq.py
+++ b/myhdl/_always_seq.py
@@ -220,7 +220,7 @@ class _SigNameVisitor(ast.NodeVisitor):
             elif self.context == OUTPUT:
                 self.outputs.add(id)
             elif self.context == INOUT:
-                raise AlwaysSeqError(_error.SigAugAssign % id)
+                raise AlwaysSeqError(_error.SigAugAssign, id)
             else:
                 raise AssertionError("bug in always_seq")