int, long

myhdl/_toVerilog/_analyze.py

@@ -108,7 +108,7 @@ def _analyzeGens(top, genNames):
             s = inspect.getsource(f)
             s = s.lstrip()
             ast = compiler.parse(s)
-            # print ast
+            print ast
             ast.sourcefile = inspect.getsourcefile(f)
             ast.lineoffset = inspect.getsourcelines(f)[1]-1
             ast.symdict = f.f_globals.copy()

myhdl/_toVerilog/_convert.py

@@ -355,6 +355,8 @@ class _ConvertVisitor(_ToVerilogMixin):
             self.require(node, val is not None, "cannot calculate len")
             self.write(`val`)
             return
+        elif f in (int, long):
+            opening, closing = '', ''
         elif type(f)  in (ClassType, type) and issubclass(f, Exception):
             self.write(f.__name__)
         elif f in (posedge, negedge):