mirror of
https://github.com/myhdl/myhdl.git
synced 2024-12-14 07:44:38 +08:00
update
This commit is contained in:
parent
d30bac487d
commit
c0ce0463da
@ -1,159 +0,0 @@
|
||||
import os
|
||||
path = os.path
|
||||
from random import randrange
|
||||
|
||||
from myhdl import *
|
||||
from myhdl.conversion import verify
|
||||
|
||||
COSET = 0x55
|
||||
|
||||
def calculateHecRef(header):
|
||||
""" Return hec for an ATM header.
|
||||
|
||||
Reference version.
|
||||
The hec polynomial is 1 + x + x**2 + x**8.
|
||||
"""
|
||||
hec = intbv(0)
|
||||
for bit in header[32:]:
|
||||
hec[8:] = concat(hec[7:2],
|
||||
bit ^ hec[1] ^ hec[7],
|
||||
bit ^ hec[0] ^ hec[7],
|
||||
bit ^ hec[7]
|
||||
)
|
||||
return hec ^ COSET
|
||||
|
||||
def calculateHecFunc(header):
|
||||
""" Return hec for an ATM header.
|
||||
|
||||
Translatable version.
|
||||
The hec polynomial is 1 + x + x**2 + x**8.
|
||||
"""
|
||||
h = intbv(0)[8:]
|
||||
for i in downrange(len(header)):
|
||||
bit = header[i]
|
||||
h[:] = concat(h[7:2],
|
||||
bit ^ h[1] ^ h[7],
|
||||
bit ^ h[0] ^ h[7],
|
||||
bit ^ h[7]
|
||||
)
|
||||
h ^= COSET
|
||||
return h
|
||||
|
||||
def calculateHecTask(hec, header):
|
||||
""" Calculate hec for an ATM header.
|
||||
|
||||
Translatable version.
|
||||
The hec polynomial is 1 + x + x**2 + x**8.
|
||||
"""
|
||||
h = intbv(0)[8:]
|
||||
for i in downrange(len(header)):
|
||||
bit = header[i]
|
||||
h[:] = concat(h[7:2],
|
||||
bit ^ h[1] ^ h[7],
|
||||
bit ^ h[0] ^ h[7],
|
||||
bit ^ h[7]
|
||||
)
|
||||
h ^= COSET
|
||||
hec[:] = h
|
||||
|
||||
def HecCalculatorPlain(hec, header):
|
||||
""" Hec calculation module.
|
||||
|
||||
Plain version.
|
||||
"""
|
||||
h = intbv(0)[8:]
|
||||
while 1:
|
||||
yield header
|
||||
h[:] = 0
|
||||
for i in downrange(len(header)):
|
||||
bit = header[i]
|
||||
h[:] = concat(h[7:2],
|
||||
bit ^ h[1] ^ h[7],
|
||||
bit ^ h[0] ^ h[7],
|
||||
bit ^ h[7]
|
||||
)
|
||||
hec.next = h ^ COSET
|
||||
|
||||
def HecCalculatorFunc(hec, header):
|
||||
""" Hec calculation module.
|
||||
|
||||
Version with function call.
|
||||
"""
|
||||
h = intbv(0)[8:]
|
||||
while 1:
|
||||
yield header
|
||||
hec.next = calculateHecFunc(header=header)
|
||||
|
||||
def HecCalculatorTask(hec, header):
|
||||
""" Hec calculation module.
|
||||
|
||||
Version with task call.
|
||||
"""
|
||||
h = intbv(0)[8:]
|
||||
while 1:
|
||||
yield header
|
||||
calculateHecTask(h, header)
|
||||
hec.next = h
|
||||
|
||||
def HecCalculatorTask2(hec, header):
|
||||
""" Hec calculation module.
|
||||
|
||||
Version with task call.
|
||||
"""
|
||||
h = intbv(0)[8:]
|
||||
while 1:
|
||||
yield header
|
||||
calculateHecTask(header=header, hec=h)
|
||||
hec.next = h
|
||||
|
||||
|
||||
|
||||
def HecCalculator_v(name, hec, header):
|
||||
return setupCosimulation(**locals())
|
||||
|
||||
|
||||
|
||||
headers = [ 0x00000000L,
|
||||
0x01234567L,
|
||||
0xbac6f4caL
|
||||
]
|
||||
|
||||
headers.extend([randrange(2**32-1) for i in range(10)])
|
||||
headers = tuple(headers)
|
||||
|
||||
|
||||
def HecBench(HecCalculator):
|
||||
|
||||
hec = Signal(intbv(0)[8:])
|
||||
hec_v = Signal(intbv(0)[8:])
|
||||
header = Signal(intbv(-1)[32:])
|
||||
|
||||
heccalc_inst = HecCalculator(hec, header)
|
||||
|
||||
@instance
|
||||
def stimulus():
|
||||
for i in range(len(headers)):
|
||||
header.next = headers[i]
|
||||
yield delay(10)
|
||||
print hec
|
||||
|
||||
return stimulus, heccalc_inst
|
||||
|
||||
## def testPlain(self):
|
||||
## sim = self.bench(HecCalculatorPlain)
|
||||
## Simulation(sim).run()
|
||||
|
||||
## def testFunc(self):
|
||||
## sim = self.bench(HecCalculatorFunc)
|
||||
## Simulation(sim).run()
|
||||
|
||||
## def testTask(self):
|
||||
## sim = self.bench(HecCalculatorTask)
|
||||
## Simulation(sim).run()
|
||||
|
||||
## def testTask2(self):
|
||||
## sim = self.bench(HecCalculatorTask2)
|
||||
## Simulation(sim).run()
|
||||
|
||||
def testPlain():
|
||||
assert verify(HecBench, HecCalculatorPlain) == 0
|
@ -1,266 +0,0 @@
|
||||
import os
|
||||
path = os.path
|
||||
from random import randrange
|
||||
|
||||
|
||||
from myhdl import *
|
||||
from myhdl.conversion import verify
|
||||
|
||||
|
||||
def ForLoop1(a, out):
|
||||
while 1:
|
||||
yield a
|
||||
var = 0
|
||||
for i in downrange(len(a)):
|
||||
if a[i] == 1:
|
||||
var += 1
|
||||
out.next = var
|
||||
|
||||
def ForLoop2(a, out):
|
||||
while 1:
|
||||
yield a
|
||||
var = 0
|
||||
for i in downrange(len(a), 5):
|
||||
if a[i] == 1:
|
||||
var += 1
|
||||
out.next = var
|
||||
|
||||
def ForLoop3(a, out):
|
||||
while 1:
|
||||
yield a
|
||||
var = 0
|
||||
for i in downrange(len(a), 3, 2):
|
||||
if a[i] == 1:
|
||||
var += 1
|
||||
out.next = var
|
||||
|
||||
def ForLoop4(a, out):
|
||||
while 1:
|
||||
yield a
|
||||
var = 0
|
||||
for i in range(len(a)):
|
||||
if a[i] == 1:
|
||||
var += 1
|
||||
out.next = var
|
||||
|
||||
def ForLoop5(a, out):
|
||||
while 1:
|
||||
yield a
|
||||
var = 0
|
||||
for i in range(6, len(a)):
|
||||
if a[i] == 1:
|
||||
var += 1
|
||||
out.next = var
|
||||
|
||||
def ForLoop6(a, out):
|
||||
while 1:
|
||||
yield a
|
||||
var = 0
|
||||
for i in range(5, len(a), 3):
|
||||
if a[i] == 1:
|
||||
var += 1
|
||||
out.next = var
|
||||
|
||||
def ForContinueLoop(a, out):
|
||||
while 1:
|
||||
yield a
|
||||
var = 0
|
||||
for i in downrange(len(a)):
|
||||
if a[i] == 0:
|
||||
continue
|
||||
var += 1
|
||||
out.next = var
|
||||
|
||||
def ForBreakLoop(a, out):
|
||||
while 1:
|
||||
yield a
|
||||
out.next = 0
|
||||
for i in downrange(len(a)):
|
||||
if a[i] == 1:
|
||||
out.next = i
|
||||
break
|
||||
|
||||
def ForBreakContinueLoop(a, out):
|
||||
while 1:
|
||||
yield a
|
||||
out.next = 0
|
||||
for i in downrange(len(a)):
|
||||
if a[i] == 0:
|
||||
continue
|
||||
out.next = i
|
||||
break
|
||||
|
||||
def NestedForLoop1(a, out):
|
||||
while 1:
|
||||
yield a
|
||||
var = 0
|
||||
for i in downrange(len(a)):
|
||||
if a[i] == 0:
|
||||
continue
|
||||
else:
|
||||
for j in downrange(i):
|
||||
if a[j] == 0:
|
||||
var +=1
|
||||
break
|
||||
out.next = var
|
||||
|
||||
def NestedForLoop2(a, out):
|
||||
while 1:
|
||||
yield a
|
||||
var = 0
|
||||
out.next = 0
|
||||
for i in downrange(len(a)):
|
||||
if a[i] == 0:
|
||||
continue
|
||||
else:
|
||||
for j in downrange(i-1):
|
||||
if a[j] == 0:
|
||||
pass
|
||||
else:
|
||||
out.next = j
|
||||
break
|
||||
break
|
||||
|
||||
def ReturnFromFunction(a):
|
||||
for i in downrange(len(a)):
|
||||
if a[i] == 1:
|
||||
return i
|
||||
return 0
|
||||
|
||||
def FunctionCall(a, out):
|
||||
while 1:
|
||||
yield a
|
||||
out.next = ReturnFromFunction(a)
|
||||
|
||||
# During the following check, I noticed that non-blocking assignments
|
||||
# are not scheduled when a task is disabled in Icarus. Apparently
|
||||
# this is one of the many vague areas in the Verilog standard.
|
||||
def ReturnFromTask(a, out):
|
||||
for i in downrange(len(a)):
|
||||
if a[i] == 1:
|
||||
out[:] = i
|
||||
return
|
||||
out[:] = 23 # to notice it
|
||||
|
||||
def TaskCall(a, out):
|
||||
var = intbv(0)[8:]
|
||||
while 1:
|
||||
yield a
|
||||
ReturnFromTask(a, var)
|
||||
out.next = var
|
||||
|
||||
def WhileLoop(a, out):
|
||||
while 1:
|
||||
yield a
|
||||
var = 0
|
||||
i = len(a)-1
|
||||
while i >= 0:
|
||||
if a[i] == 1:
|
||||
var += 1
|
||||
i -= 1
|
||||
out.next = var
|
||||
|
||||
def WhileContinueLoop(a, out):
|
||||
while 1:
|
||||
yield a
|
||||
var = 0
|
||||
i = len(a)-1
|
||||
while i >= 0:
|
||||
if a[i] == 0:
|
||||
i -= 1
|
||||
continue
|
||||
var += 1
|
||||
i -= 1
|
||||
out.next = var
|
||||
|
||||
def WhileBreakLoop(a, out):
|
||||
while 1:
|
||||
yield a
|
||||
var = 0
|
||||
i = len(a)-1
|
||||
out.next = 0
|
||||
while i >= 0:
|
||||
if a[i] == 1:
|
||||
out.next = i
|
||||
break
|
||||
i -= 1
|
||||
|
||||
def WhileBreakContinueLoop(a, out):
|
||||
while 1:
|
||||
yield a
|
||||
var = 0
|
||||
i = len(a)-1
|
||||
out.next = 0
|
||||
while i >= 0:
|
||||
if a[i] == 0:
|
||||
i -= 1
|
||||
continue
|
||||
out.next = i
|
||||
break
|
||||
|
||||
|
||||
|
||||
def LoopBench(LoopTest):
|
||||
|
||||
a = Signal(intbv(-1)[16:])
|
||||
z = Signal(intbv(0)[16:])
|
||||
|
||||
looptest_inst = LoopTest(a, z)
|
||||
data = tuple([randrange(2**min(i, 16)) for i in range(100)])
|
||||
|
||||
@instance
|
||||
def stimulus():
|
||||
for i in range(100):
|
||||
a.next = data[i]
|
||||
yield delay(10)
|
||||
print z
|
||||
|
||||
return stimulus, looptest_inst
|
||||
|
||||
|
||||
|
||||
def testForLoop1():
|
||||
assert verify(LoopBench, ForLoop1) == 0
|
||||
def testForLoop2():
|
||||
assert verify(LoopBench, ForLoop2) == 0
|
||||
def testForLoop4():
|
||||
assert verify(LoopBench, ForLoop4) == 0
|
||||
def testForLoop5():
|
||||
assert verify(LoopBench, ForLoop5) == 0
|
||||
|
||||
# for loop 3 and 6 can't work in vhdl
|
||||
|
||||
def testForContinueLoop():
|
||||
assert verify(LoopBench, ForContinueLoop) == 0
|
||||
|
||||
def testForBreakLoop():
|
||||
assert verify(LoopBench, ForBreakLoop) == 0
|
||||
|
||||
def testForBreakContinueLoop():
|
||||
assert verify(LoopBench, ForBreakContinueLoop) == 0
|
||||
|
||||
def testNestedForLoop1():
|
||||
assert verify(LoopBench, NestedForLoop1) == 0
|
||||
|
||||
def testNestedForLoop2():
|
||||
assert verify(LoopBench, NestedForLoop2) == 0
|
||||
|
||||
def testWhileLoop():
|
||||
assert verify(LoopBench, FunctionCall) == 0
|
||||
|
||||
## def testTaskCall(self):
|
||||
## sim = self.bench(TaskCall)
|
||||
## Simulation(sim).run()
|
||||
|
||||
def testWhileLoop():
|
||||
assert verify(LoopBench, WhileLoop) == 0
|
||||
|
||||
def testWhileContinueLoop():
|
||||
assert verify(LoopBench, WhileContinueLoop) == 0
|
||||
|
||||
def testWhileBreakLoop():
|
||||
assert verify(LoopBench, WhileBreakLoop) == 0
|
||||
|
||||
def testWhileBreakContinueLoop():
|
||||
assert verify(LoopBench, WhileBreakContinueLoop) == 0
|
||||
|
@ -120,6 +120,7 @@ def RamBench(ram, depth=128):
|
||||
@instance
|
||||
def stimulus():
|
||||
for i in range(depth):
|
||||
yield clk.negedge
|
||||
din.next = i
|
||||
addr.next = i
|
||||
we.next = True
|
||||
@ -127,7 +128,6 @@ def RamBench(ram, depth=128):
|
||||
we.next = False
|
||||
for i in range(depth):
|
||||
addr.next = i
|
||||
yield clk.negedge
|
||||
yield clk.posedge
|
||||
yield delay(1)
|
||||
assert dout == i
|
||||
|
@ -1,100 +0,0 @@
|
||||
import os
|
||||
path = os.path
|
||||
from random import randrange
|
||||
|
||||
from myhdl import *
|
||||
|
||||
D = 256
|
||||
|
||||
ROM = tuple([randrange(D) for i in range(D)])
|
||||
|
||||
def rom1(dout, addr, clk):
|
||||
|
||||
def rdLogic() :
|
||||
while 1:
|
||||
yield clk.posedge
|
||||
dout.next = ROM[int(addr)]
|
||||
|
||||
RL = rdLogic()
|
||||
return RL
|
||||
|
||||
def rom2(dout, addr, clk):
|
||||
|
||||
theROM = ROM
|
||||
|
||||
def rdLogic() :
|
||||
while 1:
|
||||
yield clk.posedge
|
||||
dout.next = theROM[int(addr)]
|
||||
|
||||
RL = rdLogic()
|
||||
return RL
|
||||
|
||||
|
||||
def rom3(dout, addr, clk):
|
||||
|
||||
|
||||
def rdLogic() :
|
||||
tmp = intbv(0)[8:]
|
||||
while 1:
|
||||
yield addr
|
||||
tmp[:] = ROM[int(addr)]
|
||||
dout.next = tmp
|
||||
|
||||
RL = rdLogic()
|
||||
return RL
|
||||
|
||||
def rom4(dout, addr, clk):
|
||||
|
||||
@always_comb
|
||||
def read():
|
||||
dout.next = ROM[int(addr)]
|
||||
|
||||
return read
|
||||
|
||||
|
||||
|
||||
def RomBench(rom):
|
||||
|
||||
dout = Signal(intbv(0)[8:])
|
||||
addr = Signal(intbv(1)[8:])
|
||||
clk = Signal(bool(0))
|
||||
|
||||
rom_inst = rom(dout, addr, clk)
|
||||
|
||||
@instance
|
||||
def stimulus():
|
||||
for i in range(D):
|
||||
addr.next = i
|
||||
yield clk.negedge
|
||||
yield clk.posedge
|
||||
yield delay(1)
|
||||
assert dout == ROM[i]
|
||||
print dout
|
||||
raise StopSimulation()
|
||||
|
||||
@instance
|
||||
def clkgen():
|
||||
clk.next = 1
|
||||
while 1:
|
||||
yield delay(10)
|
||||
clk.next = not clk
|
||||
|
||||
return clkgen, stimulus, rom_inst
|
||||
|
||||
def test1():
|
||||
assert conversion.verify(RomBench, rom1) == 0
|
||||
|
||||
def test2():
|
||||
assert conversion.verify(RomBench, rom2) == 0
|
||||
|
||||
def test3():
|
||||
assert conversion.verify(RomBench, rom3) == 0
|
||||
|
||||
def test4():
|
||||
assert conversion.verify(RomBench, rom4) == 0
|
||||
|
||||
|
||||
|
||||
|
||||
|
Loading…
x
Reference in New Issue
Block a user