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Remove unsupported type check in _analyze.py since it is already done in _toVerilog,_toVHDL

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This commit is contained in:
Keerthan Jaic 2015-01-17 23:27:37 -05:00
parent 5d4ebcdf0c
commit c2021eb8c7
1 changed files with 0 additions and 8 deletions
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8
myhdl/conversion/_analyze.py
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@ -181,14 +181,6 @@ def _analyzeGens(top, absnames):
v = _FirstPassVisitor(tree)
v.visit(tree)
if isinstance(g, _AlwaysComb):
objs = [tree.symdict[objname] for objname in tree.objlist]
for obj in objs:
if not ( isinstance(obj, (int, long, EnumType,_Signal)) or \
_isMem(obj) or _isTupleOfInts(obj)
):
info = "File %s, line %s: " % (tree.sourcefile, tree.lineoffset)
print type(obj)
raise ConversionError(_error.UnsupportedType, n, info)
v = _AnalyzeAlwaysCombVisitor(tree, g.senslist)
elif isinstance(g, _AlwaysSeq):
v = _AnalyzeAlwaysSeqVisitor(tree, g.senslist, g.reset, g.sigregs, g.varregs)