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Merge pull request #115 from cfelton/verilog_inout

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Added inout pot declaration to Verilog conversion for TristateSignals
This commit is contained in:
jandecaluwe 2015-07-28 14:23:43 +02:00
commit c7d92c471c
1 changed files with 4 additions and 1 deletions
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myhdl/conversion/_toVerilog.py
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@ -258,7 +258,10 @@ def _writeModuleHeader(f, intf, doc):
warnings.warn("%s: %s" % (_error.OutputPortRead, portname),
category=ToVerilogWarning
)
print("output %s%s%s;" % (p, r, portname), file=f)
if isinstance(s, _TristateSignal):
print("inout %s%s%s;" % (p, r, portname), file=f)
else:
print("output %s%s%s;" % (p, r, portname), file=f)
if s._driven == 'reg':
print("reg %s%s%s;" % (p, r, portname), file=f)
else: