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binary op debug

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This commit is contained in:
jand 2006-11-07 13:59:23 +00:00
parent 39a2603d92
commit c7fc9d7633
2 changed files with 27 additions and 12 deletions
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13
myhdl/conversion/_toVHDL.py
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@ -437,12 +437,17 @@ class _ConvertVisitor(_ConversionMixin):
else:
self.raiseError(node, "Not implemented")
elif isinstance(l, vhd_unsigned) and isinstance(r, (vhd_int, vhd_unsigned)):
print "HERE1"
print op
if ds < 0:
nc.pre, nc.suf = "resize(", ", %s)" % ns
elif ds > 0:
print "HERE"
print op
if op in ('+', '-', '/'):
lc.pre, lc.suf = "resize(", ", %s)" % ns
elif op in ('mod'):
elif op in ('mod', ):
print 'MOD HERE'
nc.pre, nc.suf = "resize(", ", %s)" % ns
else:
self.raiseError(node, "Not implemented")
@ -1601,7 +1606,7 @@ class _AnnotateTypesVisitor(_ConversionMixin):
node.expr.vhd = vhd_int()
node.vhdOri = node.vhd
else:
r, l = node.node.vhd, node.expr.vhd
l, r = node.node.vhd, node.expr.vhd
self.inferBinaryOpType(node, l, r, node.op)
node.vhdOri = node.vhd
node.vhd = node.node.vhd
@ -1668,8 +1673,8 @@ class _AnnotateTypesVisitor(_ConversionMixin):
node.vhdOri = node.vhd
def inferBinaryOpType(self, node, r, l, op=None):
rs, ls = r.size, l.size
def inferBinaryOpType(self, node, l, r, op=None):
ls, rs = l.size, r.size
if isinstance(r, vhd_signed) and isinstance(r, vhd_unsigned):
rs += 1
if isinstance(r, vhd_unsigned) and isinstance(r, vhd_signed):

26
myhdl/test/toVHDL/test_ops.py
View File

@ -40,8 +40,8 @@ def binaryOps(
## if left < 256 and right < 40:
if left < 256 and right < 26: # fails in ghdl for > 26
LeftShift.next = left << right
## if right != 0:
## Modulo.next = left % right
if right != 0:
Modulo.next = left % right
Mul.next = left * right
# Icarus doesn't support ** yet
#if left < 256 and right < 40:
@ -144,9 +144,9 @@ def binaryBench(m, n):
print FloorDiv
print LeftShift
## print Modulo, Modulo_v)
## # print Pow, Pow_v)
# print Pow, Pow_v
print Modulo
print RightShift
print Mul
print Sub
@ -403,14 +403,24 @@ def augmBench(m, n):
left, right)
def stimulus():
left.next = 1
right.next = 1
yield delay(10)
left.next = 0
right.next = 0
yield delay(10)
left.next = 0
right.next = N-1
yield delay(10)
left.next = M-1
right.next = 0
yield delay(10)
left.next = M-1
right.next = N-1
for i in range(NRTESTS):
left.next = seqM[i]
right.next = seqN[i]
yield delay(10)
## for j, k in ((0, 0), (0, N-1), (M-1, 0), (M-1, N-1)):
## left.next = j
## right.next = k
## yield delay(10)
def check():