diff --git a/cosimulation/icarus/myhdl.c b/cosimulation/icarus/myhdl.c
index 6f0ca48b..6f6c368e 100644
--- a/cosimulation/icarus/myhdl.c
+++ b/cosimulation/icarus/myhdl.c
@@ -226,7 +226,7 @@ static PLI_INT32 to_myhdl_readonly_callback(p_cb_data cb_data)
   vpiHandle net_iter, net_handle;
   vpiHandle reg_iter, reg_handle;
   s_cb_data cb_data_s;
-  s_vpi_time verilog_time;
+  s_vpi_time verilog_time_s;
   s_vpi_value value_s;
   s_vpi_time time_s;
   char buf[MAXLINE];
@@ -245,11 +245,13 @@ static PLI_INT32 to_myhdl_readonly_callback(p_cb_data cb_data)
     assert(n > 0);
   }
 
-  net_iter = vpi_iterate(vpiArgument, to_myhdl_systf_handle);
   buf[0] = '\0';
-  verilog_time.type = vpiSimTime;
-  vpi_get_time(systf_handle, &verilog_time);
-  sprintf(buf, "%xd%08x ", verilog_time.high, verilog_time.low);
+  verilog_time_s.type = vpiSimTime;
+  vpi_get_time(NULL, &verilog_time_s);
+  verilog_time = timestruct_to_time(&verilog_time_s);
+  assert(verilog_time == pli_time * 1000 + delta);
+  sprintf(buf, "%llu ", pli_time);
+  net_iter = vpi_iterate(vpiArgument, to_myhdl_systf_handle);
   value_s.format = vpiHexStrVal;
   while ((net_handle = vpi_scan(net_iter)) != NULL) {
     vpi_get_value(net_handle, &value_s);
diff --git a/cosimulation/icarus/test/test_all.py b/cosimulation/icarus/test/test_all.py
index 6a0ca1a7..e64ed3d5 100644
--- a/cosimulation/icarus/test/test_all.py
+++ b/cosimulation/icarus/test/test_all.py
@@ -30,8 +30,6 @@ sys.path.append("../../test")
 import test_bin2gray, test_inc
 
 modules = (test_bin2gray, test_inc)
-modules = (test_bin2gray, )
-modules = (test_inc, )
 
 import unittest
 
diff --git a/cosimulation/test/test_bin2gray.py b/cosimulation/test/test_bin2gray.py
index 4a1c8ebc..fb46e64d 100644
--- a/cosimulation/test/test_bin2gray.py
+++ b/cosimulation/test/test_bin2gray.py
@@ -16,11 +16,6 @@ def nextLn(Ln):
     Ln1.reverse()
     return Ln0 + Ln1
 
-## def bin2gray(B, G, width):
-##     while 1:
-##         yield B
-##         G.next = B[0]
-
 class TestOriginalGrayCode(TestCase):
 
     def testOriginalGrayCode(self):
@@ -72,7 +67,7 @@ class TestGrayCodeProperties(TestCase):
             dut = bin2gray(B, G, width)
             check = test(B, G, G_Z, width)
             sim = Simulation(dut, check)
-            sim.run(quiet=0)
+            sim.run(quiet=1)
 
 
     def testUniqueCodeWords(self):
diff --git a/cosimulation/test/test_inc.py b/cosimulation/test/test_inc.py
index 16cba2a1..9e3f34b0 100644
--- a/cosimulation/test/test_inc.py
+++ b/cosimulation/test/test_inc.py
@@ -34,7 +34,7 @@ class TestInc(TestCase):
             reset.next = ACTIVE_LOW
             yield negedge(clock)
             reset.next = INACTIVE_HIGH
-            for i in range(20):
+            for i in range(1000):
                 enable.next = min(1, randrange(5))
                 yield negedge(clock)
             raise StopSimulation
@@ -48,7 +48,7 @@ class TestInc(TestCase):
                 if enable:
                     expect = (expect + 1) % n
                 yield delay(1)
-                print "%d count %s expect %s" % (now(), count, expect)
+                # print "%d count %s expect %s" % (now(), count, expect)
                 self.assertEqual(count, expect)
 
         Simulation(clockGen(), stimulus(), INC_1, check()).run(quiet=1)        
diff --git a/cosimulation/test/verilog/inc.v b/cosimulation/test/verilog/inc.v
index df1a82c0..6ab43705 100644
--- a/cosimulation/test/verilog/inc.v
+++ b/cosimulation/test/verilog/inc.v
@@ -9,10 +9,8 @@ module inc(count, enable, clock, reset);
 
    initial
      count = 0;
-   
 
    always @(posedge clock or negedge reset) begin
-      // $display("Always triggered: count %d", count);
       if (reset == 0) begin
 	 count <= 0;
       end
@@ -20,14 +18,11 @@ module inc(count, enable, clock, reset);
 	 if (enable) begin
 	    count <= (count + 1) % n;
 	 end
-	 // $display("count %d", count);
       end
    end // always @ (posedge clock or negedge reset)
 
-   always @ (count) begin
-	 $display("%d count %d", $time, count);
-   end
-   
-      
+//   always @ (count) begin
+//	 $display("%d count %d", $time, count);
+//   end
 
 endmodule // inc
diff --git a/myhdl/Cosimulation.py b/myhdl/Cosimulation.py
index e88692a7..3d7fe35d 100644
--- a/myhdl/Cosimulation.py
+++ b/myhdl/Cosimulation.py
@@ -136,11 +136,9 @@ class Cosimulation(object):
                     break
                 else:
                     raise Error, "Unexpected cosim input"
-            # os.waitpid(child_pid, 0)
 
     def _get(self):
         s = os.read(self._rt, _MAXLINE)
-        # print "Reading " + s
         if not s:
             raise SimulationEndError
         e = s.split()
@@ -157,23 +155,18 @@ class Cosimulation(object):
         buf = repr(time)
         if buf[-1] == 'L':
             buf = buf[:-1] # strip trailing L
-        if self._isActive:
-            self._isActive -= 1
         if self._hasChange:
             self._hasChange = 0
             for s in self._fromSigs:
                 buf += " "
                 buf += hex(s)[2:]
-        # print "Writing " + buf
         os.write(self._wf, buf)
 
     def _waiter(self):
         sigs = tuple(self._fromSigs)
         while 1:
             yield sigs
-            # print sigs
             self._hasChange = 1
-            self._isActive = 1
             
     def __del__(self):
         """ Clear flag when this object destroyed - to suite unittest. """
diff --git a/myhdl/test_Cosimulation.py b/myhdl/test_Cosimulation.py
index 3c97393f..c7294107 100644
--- a/myhdl/test_Cosimulation.py
+++ b/myhdl/test_Cosimulation.py
@@ -218,7 +218,7 @@ class CosimulationTest(TestCase):
         os.read(rf, MAXLINE)
         os.write(wt, "DUMMY")
         s = os.read(rf, MAXLINE)
-        vals = [long(e, 16) for e in s.split()[2:]]
+        vals = [long(e, 16) for e in s.split()[1:]]
         self.assertEqual(vals, fromVals)
 
     def testToSignalVals(self):