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UNSTABLE - replace compiler by ast

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All unit tests for Verilog conversion work.
This commit is contained in:
Jan Decaluwe 2009-05-03 10:38:52 +02:00
parent e6ba8d4ec1
commit cad761f30d
3 changed files with 23 additions and 12 deletions
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7
myhdl/conversion/_analyze.py
View File

@ -448,7 +448,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
# self.multiLogicalOp(node, *args) # self.multiLogicalOp(node, *args)
def visit_Boolop(self, node): def visit_BoolOp(self, node):
for n in node.values: for n in node.values:
self.visit(n) self.visit(n)
for n in node.values: for n in node.values:
@ -1629,7 +1629,7 @@ class _AnalyzeBlockVisitor(_AnalyzeVisitor):
def visit_Return(self, node): def visit_Return(self, node):
### value should be None ### value should be None
if not node.value is None: if node.value is None:
pass pass
elif isinstance(node.value, ast.Name) and node.value.id == "None": elif isinstance(node.value, ast.Name) and node.value.id == "None":
pass pass
@ -1812,7 +1812,8 @@ class _AnalyzeFuncVisitor(_AnalyzeVisitor):
def visit_Return(self, node): def visit_Return(self, node):
self.kind = _kind.DECLARATION self.kind = _kind.DECLARATION
self.visit(node.value) if node.value is not None:
self.visit(node.value)
self.kind = _kind.NORMAL self.kind = _kind.NORMAL
if node.value is None: if node.value is None:
obj = None obj = None

20
myhdl/conversion/_misc.py
View File

@ -83,14 +83,20 @@ _context = enum("BOOLEAN", "YIELD", "PRINT" ,"SIGNED", "UNKNOWN")
class _ConversionMixin(object): class _ConversionMixin(object):
# def getLineNo(self, node):
# lineno = node.lineno
# if lineno is None:
# for n in node.getChildNodes():
# if n.lineno is not None:
# lineno = n.lineno
# break
# lineno = lineno or 0
# return lineno
def getLineNo(self, node): def getLineNo(self, node):
lineno = node.lineno lineno = 0
if lineno is None: if isinstance(node, (ast.stmt, ast.expr)):
for n in node.getChildNodes(): lineno = node.lineno
if n.lineno is not None:
lineno = n.lineno
break
lineno = lineno or 0
return lineno return lineno
def getObj(self, node): def getObj(self, node):

8
myhdl/conversion/_toVerilog.py
View File

@ -324,7 +324,7 @@ opmap = {
ast.Mod : '%', ast.Mod : '%',
ast.Pow : '**', ast.Pow : '**',
ast.LShift : '<<', ast.LShift : '<<',
ast.RShift : '>>', ast.RShift : '>>>',
ast.BitOr : '|', ast.BitOr : '|',
ast.BitAnd : '&', ast.BitAnd : '&',
ast.BitXor : '^', ast.BitXor : '^',
@ -339,6 +339,8 @@ opmap = {
ast.Lt : '<', ast.Lt : '<',
ast.LtE : '<=', ast.LtE : '<=',
ast.NotEq : '!=', ast.NotEq : '!=',
ast.And : '&&',
ast.Or : '||',
} }
@ -533,7 +535,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
def visit_BoolOp(self, node): def visit_BoolOp(self, node):
self.write("(") self.write("(")
self.visit(node.values[0]) self.visit(node.values[0])
for n in node.nodes[1:]: for n in node.values[1:]:
self.write(" %s " % opmap[type(node.op)]) self.write(" %s " % opmap[type(node.op)])
self.visit(n) self.visit(n)
self.write(")") self.write(")")
@ -1537,6 +1539,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
addSignBit = isinstance(node.ctx, ast.Load) and (self.context == _context.SIGNED) addSignBit = isinstance(node.ctx, ast.Load) and (self.context == _context.SIGNED)
if addSignBit: if addSignBit:
self.write("$signed({1'b0, ") self.write("$signed({1'b0, ")
self.context = None
self.visit(node.value) self.visit(node.value)
lower, upper = node.slice.lower, node.slice.upper lower, upper = node.slice.lower, node.slice.upper
# special shortcut case for [:] slice # special shortcut case for [:] slice
@ -1563,6 +1566,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
(self.context == _context.SIGNED) (self.context == _context.SIGNED)
if addSignBit: if addSignBit:
self.write("$signed({1'b0, ") self.write("$signed({1'b0, ")
self.context = None
self.visit(node.value) self.visit(node.value)
self.write("[") self.write("[")
# assert len(node.subs) == 1 # assert len(node.subs) == 1