FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00
Code Issues Projects Releases Wiki Activity

Update _traceSignals.py

Browse Source
This commit is contained in:
Nicolas Pinault 2018-02-28 09:59:09 +01:00 committed by GitHub
parent 512dfaa17c
commit cb422c7909
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 0 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
myhdl/_traceSignals.py
View File

@ -68,8 +68,6 @@ class _TraceSignalsClass(object):
def __call__(self, dut, *args, **kwargs):
global _tracing, vcdpath
if 'timescale' in kwargs:
self.timescale = kwargs['timescale']
if isinstance(dut, _Block):
# now we go bottom-up: so clean up and start over
# TODO: consider a warning for the overruled block