FPGA/myhdl
1
0
Fork 0
mirror of https://github.com/myhdl/myhdl.git synced 2024-12-14 07:44:38 +08:00
Code Issues Projects Releases Wiki Activity

README update

Browse Source
This commit is contained in:
Jan Decaluwe 2013-05-20 18:28:07 +02:00
parent 91891cea4b
commit cb6760af95
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
myhdl/test/bugs/README.txt
View File

@ -1,5 +1,5 @@
Requirements: Requirements:
* cver, icarus, or GHDL * cver, icarus, GHDL or vlog/vcom (default)
* py.test * py.test
See the Makefile - it contains targets per simulator. See the Makefile - it contains targets per simulator.