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https://github.com/myhdl/myhdl.git
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signed binary ops
This commit is contained in:
jand
parent
a0289a4fe8
commit
cbef36f877
@ -1748,6 +1748,10 @@ class _AnnotateTypesVisitor(_ConversionMixin):
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def inferBinaryOpType(self, node, left, right, op=None):
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if isinstance(left.vhd, (vhd_boolean, vhd_std_logic)):
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left.vhd = vhd_unsigned(1)
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if isinstance(right.vhd, (vhd_boolean, vhd_std_logic)):
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right.vhd = vhd_unsigned(1)
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if maybeNegative(left.vhd) and isinstance(right.vhd, vhd_unsigned):
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right.vhd = vhd_signed(right.vhd.size + 1)
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if isinstance(left.vhd, vhd_unsigned) and maybeNegative(right.vhd):
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@ -7,235 +7,192 @@ random.seed(2)
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from myhdl import *
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NRTESTS = 10
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def binaryOps(
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## Bitand,
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## Bitor,
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## Bitxor,
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## FloorDiv,
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LeftShift,
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## Mod,
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Mul,
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## Pow,
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RightShift,
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Sub,
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Sum, Sum1, Sum2, Sum3,
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EQ,
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NE,
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LT,
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GT,
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LE,
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GE,
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BoolAnd,
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BoolOr,
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left, right, bit):
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## def binaryOps(
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## ## Bitand,
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## ## Bitor,
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## ## Bitxor,
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## ## FloorDiv,
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## LeftShift,
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## ## Mod,
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## Mul,
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## ## Pow,
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## RightShift,
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## Sub,
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## Sum, Sum1, Sum2, Sum3,
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## EQ,
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## NE,
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## LT,
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## GT,
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## LE,
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## GE,
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## And,
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## Or,
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## left, right, bit):
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## while 1:
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## yield left, right
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## ## Bitand.next = left & right
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## ## Bitor.next = left | right
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## ## Bitxor.next = left ^ right
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## ## if right != 0:
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## ## FloorDiv.next = left // right
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while 1:
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yield left, right
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## Bitand.next = left & right
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## Bitor.next = left | right
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## Bitxor.next = left ^ right
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## if right != 0:
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## FloorDiv.next = left // right
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## if left < 256 and right < 40 and right >= 0:
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## LeftShift.next = left << right
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## ## if right != 0:
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## ## Mod.next = left % right
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## if right != 0:
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## Mod.next = left % right
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## Mul.next = left * right
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## ## # Icarus doesn't support ** yet
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## ## #if left < 256 and right < 40:
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## ## # Pow.next = left ** right
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## ## Pow.next = 0
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## # Icarus doesn't support ** yet
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## #if left < 256 and right < 40:
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## # Pow.next = left ** right
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## Pow.next = 0
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## if right >= -0:
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## RightShift.next = left >> right
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## ## RightShift.next = left
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## Sub.next = left - right
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## Sum.next = left + right
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## RightShift.next = left
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Sub.next = left - right
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Sum.next = left + right
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## Sum1.next = left + right[2:]
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## Sum2.next = left + right[1]
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## Sum3.next = left + bit
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## EQ.next = left == right
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## NE.next = left != right
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## LT.next = left < right
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## GT.next = left > right
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## LE.next = left <= right
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## GE.next = left >= right
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## And.next = bool(left) and bool(right)
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## Or.next = bool(left) or bool(right)
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EQ.next = left == right
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NE.next = left != right
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LT.next = left < right
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GT.next = left > right
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LE.next = left <= right
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GE.next = left >= right
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BoolAnd.next = bool(left) and bool(right)
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BoolOr.next = bool(left) or bool(right)
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## def binaryOps_v(name,
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## ## Bitand,
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## ## Bitor,
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## ## Bitxor,
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## ## FloorDiv,
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## LeftShift,
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## ## Mod,
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## Mul,
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## ## Pow,
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## RightShift,
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## Sub,
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## Sum, Sum1, Sum2, Sum3,
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## EQ,
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## NE,
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## LT,
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## GT,
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## LE,
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## GE,
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## And,
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## Or,
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## left, right, bit):
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## return setupCosimulation(**locals())
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def binaryBench(Ll, Ml, Lr, Mr):
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## class TestBinaryOps(TestCase):
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seqL = []
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seqR = []
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for i in range(NRTESTS):
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seqL.append(randrange(Ll, Ml))
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seqR.append(randrange(Lr, Mr))
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for j, k in ((Ll, Lr), (Ml-1, Mr-1), (Ll, Mr-1), (Ml-1, Lr)):
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seqL.append(j)
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seqR.append(k)
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seqL = tuple(seqL)
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seqR = tuple(seqR)
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## def binaryBench(self, Ll, Ml, Lr, Mr):
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bit = Signal(bool(0))
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left = Signal(intbv(min=Ll, max=Ml))
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right = Signal(intbv(min=Lr, max=Mr))
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M = 2**14
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## Bitand = Signal(intbv(0, min=-2**17, max=2**17))
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## Bitand_v = Signal(intbv(0, min=-2**17, max=2**17))
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## Bitor = Signal(intbv(0)[max(m, n):])
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## Bitor_v = Signal(intbv(0)[max(m, n):])
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## Bitxor = Signal(intbv(0)[max(m, n):])
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## Bitxor_v = Signal(intbv(0)[max(m, n):])
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## FloorDiv = Signal(intbv(0)[m:])
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## FloorDiv_v = Signal(intbv(0)[m:])
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LeftShift = Signal(intbv(0, min=-2**64, max=2**64))
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## Mod = Signal(intbv(0)[m:])
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Mul = Signal(intbv(0, min=-2**17, max=2**17))
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## Pow = Signal(intbv(0)[64:])
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RightShift = Signal(intbv(0, min=-M, max=M))
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Sub, Sub1, Sub2, Sub3 = [Signal(intbv(min=-M, max=M)) for i in range(4)]
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Sum, Sum1, Sum2, Sum3 = [Signal(intbv(min=-M, max=M)) for i in range(4)]
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EQ, NE, LT, GT, LE, GE = [Signal(bool()) for i in range(6)]
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BoolAnd, BoolOr = [Signal(bool()) for i in range(2)]
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## bit = Signal(bool(0))
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## left = Signal(intbv(min=Ll, max=Ml))
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## right = Signal(intbv(min=Lr, max=Mr))
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## M = 2**14
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## ## Bitand = Signal(intbv(0, min=-2**17, max=2**17))
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## ## Bitand_v = Signal(intbv(0, min=-2**17, max=2**17))
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## ## Bitor = Signal(intbv(0)[max(m, n):])
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## ## Bitor_v = Signal(intbv(0)[max(m, n):])
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## ## Bitxor = Signal(intbv(0)[max(m, n):])
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## ## Bitxor_v = Signal(intbv(0)[max(m, n):])
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## ## FloorDiv = Signal(intbv(0)[m:])
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## ## FloorDiv_v = Signal(intbv(0)[m:])
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## LeftShift = Signal(intbv(0, min=-2**64, max=2**64))
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## LeftShift_v = Signal(intbv(0, min=-2**64, max=2**64))
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## ## Mod = Signal(intbv(0)[m:])
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## ## Mod_v = Signal(intbv(0)[m:])
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## Mul = Signal(intbv(0, min=-2**17, max=2**17))
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## Mul_v = Signal(intbv(0, min=-2**17, max=2**17))
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## ## Pow = Signal(intbv(0)[64:])
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## ## Pow_v = Signal(intbv(0)[64:])
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## RightShift = Signal(intbv(0, min=-M, max=M))
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## RightShift_v = Signal(intbv(0, min=-M, max=M))
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## Sub, Sub1, Sub2, Sub3 = [Signal(intbv(min=-M, max=M)) for i in range(4)]
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## Sub_v, Sub1_v, Sub2_v, Sub3_v = [Signal(intbv(min=-M, max=M)) for i in range(4)]
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## Sum, Sum1, Sum2, Sum3 = [Signal(intbv(min=-M, max=M)) for i in range(4)]
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## Sum_v, Sum1_v, Sum2_v, Sum3_v = [Signal(intbv(min=-M, max=M)) for i in range(4)]
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## EQ, NE, LT, GT, LE, GE = [Signal(bool()) for i in range(6)]
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## EQ_v, NE_v, LT_v, GT_v, LE_v, GE_v = [Signal(bool()) for i in range(6)]
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## And, Or = [Signal(bool()) for i in range(2)]
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## And_v, Or_v, = [Signal(bool()) for i in range(2)]
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binops = binaryOps(
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## Bitand,
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## Bitor,
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## Bitxor,
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## FloorDiv,
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LeftShift,
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## Mod,
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Mul,
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## Pow,
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RightShift,
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Sub,
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Sum, Sum1, Sum2, Sum3,
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EQ,
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NE,
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LT,
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GT,
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LE,
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GE,
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BoolAnd,
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BoolOr,
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left, right, bit)
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## binops = toVerilog(binaryOps,
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## ## Bitand,
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## ## Bitor,
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## ## Bitxor,
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## ## FloorDiv,
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## LeftShift,
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## ## Mod,
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## Mul,
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## ## Pow,
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## RightShift,
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## Sub,
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## Sum, Sum1, Sum2, Sum3,
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## EQ,
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## NE,
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## LT,
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## GT,
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## LE,
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## GE,
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## And,
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## Or,
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## left, right, bit)
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## binops_v = binaryOps_v(binaryOps.func_name,
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## ## Bitand_v,
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## ## Bitor_v,
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## ## Bitxor_v,
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## ## FloorDiv_v,
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## LeftShift_v,
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## ## Mod_v,
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## Mul_v,
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## ## Pow_v,
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## RightShift_v,
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## Sub_v,
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## Sum_v, Sum1_v, Sum2_v, Sum3_v,
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## EQ_v,
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## NE_v,
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## LT_v,
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## GT_v,
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## LE_v,
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## GE_v,
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## And_v,
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## Or_v,
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## left, right, bit)
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## def stimulus():
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## for i in range(100):
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## bit.next = False
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## left.next = randrange(Ll, Ml)
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## right.next = randrange(Lr, Mr)
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## yield delay(10)
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## for j, k in ((Ll, Lr), (Ml-1, Mr-1), (Ll, Mr-1), (Ml-1, Lr)):
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## left.next = j
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## right.next = k
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## yield delay(10)
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def stimulus():
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for i in range(len(seqL)):
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left.next = seqL[i]
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right.next = seqR[i]
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yield delay(10)
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## def check():
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## while 1:
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## yield left, right
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## bit.next = not bit
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## yield delay(1)
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def check():
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while 1:
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yield left, right
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bit.next = not bit
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yield delay(1)
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## #print "%s %s %s %s" % (left, right, Mul, Mul_v)
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## #print "%s %s %s %s" % (left, right, bin(Mul), bin(Mul_v))
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## #print "%s %s %s %s" % (left, right, Sum, Sum_v)
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## #print "%s %s %s %s" % (left, right, bin(Sum), bin(Sum_v))
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## ## print left
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## ## print right
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## ## print bin(left)
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## ## print bin(right)
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## ## print bin(Bitand)
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## ## print bin(Bitand_v)
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## ## print Bitand
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## ## print Bitand_v
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## ## self.assertEqual(Bitand, Bitand_v)
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## #w = len(Bitand)
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## #self.assertEqual(bin(Bitand, w), bin(Bitand_v,w ))
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## ## self.assertEqual(Bitor, Bitor_v)
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## ## self.assertEqual(Bitxor, Bitxor_v)
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#print "%s %s %s %s" % (left, right, Mul, Mul_v)
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#print "%s %s %s %s" % (left, right, bin(Mul), bin(Mul_v))
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#print "%s %s %s %s" % (left, right, Sum, Sum_v)
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#print "%s %s %s %s" % (left, right, bin(Sum), bin(Sum_v))
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## print left
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## print right
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## print bin(left)
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## print bin(right)
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## print bin(Bitand)
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## print bin(Bitand_v)
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## print Bitand
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## print Bitand_v
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## self.assertEqual(Bitand, Bitand_v)
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#w = len(Bitand)
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#self.assertEqual(bin(Bitand, w), bin(Bitand_v,w ))
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## self.assertEqual(Bitor, Bitor_v)
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## self.assertEqual(Bitxor, Bitxor_v)
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## ## self.assertEqual(FloorDiv, FloorDiv_v)
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## self.assertEqual(LeftShift, LeftShift_v)
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## ## self.assertEqual(Mod, Mod_v)
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## self.assertEqual(Mul, Mul_v)
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## # self.assertEqual(Pow, Pow_v)
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## self.assertEqual(RightShift, RightShift_v)
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## self.assertEqual(Sub, Sub_v)
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## self.assertEqual(Sum, Sum_v)
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## self.assertEqual(Sum1, Sum1_v)
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## self.assertEqual(Sum2, Sum2_v)
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## self.assertEqual(Sum3, Sum3_v)
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## self.assertEqual(EQ, EQ_v)
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## self.assertEqual(NE, NE_v)
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## self.assertEqual(LT, LT_v)
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## self.assertEqual(GT, GT_v)
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## self.assertEqual(LE, LE_v)
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## self.assertEqual(GE, GE_v)
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## self.assertEqual(And, And_v)
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## self.assertEqual(Or, Or_v)
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## print LeftShift
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## self.assertEqual(Mod, Mod_v)
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## print Mul
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# self.assertEqual(Pow, Pow_v)
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## print RightShift
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print Sub
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print Sum
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## print Sum1
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## print Sum2
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## print Sum3
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print int(EQ)
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print int(NE)
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print int(LT)
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print int(GT)
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print int(LE)
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print int(GE)
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print int(BoolAnd)
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print int(BoolOr)
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## return binops, binops_v, stimulus(), check()
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return binops, stimulus(), check()
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## def testBinaryOps(self):
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## for Ll, Ml, Lr, Mr in (
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## (-254, 236, 0, 4),
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## (-128, 128, -128, 128),
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## (-53, 25, -23, 123),
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## (-23, 145, -66, 12),
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## (23, 34, -34, -16),
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## (-54, -20, 45, 73),
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## (-25, -12, -123, -66),
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## ):
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## sim = self.binaryBench(Ll, Ml, Lr, Mr)
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## Simulation(sim).run()
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def checkBinaryOps( Ll, Ml, Lr, Mr):
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assert conversion.verify(binaryBench, Ll, Ml, Lr, Mr ) == 0
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def testBinaryOps():
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for Ll, Ml, Lr, Mr in (
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(-254, 236, 0, 4),
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(-128, 128, -128, 128),
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(-53, 25, -23, 123),
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(-23, 145, -66, 12),
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(23, 34, -34, -16),
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(-54, -20, 45, 73),
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(-25, -12, -123, -66),
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):
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yield checkBinaryOps, Ll, Ml, Lr, Mr
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@ -171,7 +171,7 @@ class TestBinaryOps(TestCase):
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def stimulus():
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for i in range(100):
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bit.next = False
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# bit.next = False
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left.next = randrange(Ll, Ml)
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right.next = randrange(Lr, Mr)
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yield delay(10)
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