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port usage warnings

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This commit is contained in:
jand 2007-11-13 20:44:35 +00:00
parent 904e79d824
commit cec118c858
5 changed files with 23 additions and 4 deletions
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3
myhdl/conversion/_analyze.py
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@ -620,7 +620,8 @@ class _AnalyzeVisitor(_ConversionMixin):
def visitGetattr(self, node, *args):
self.visit(node.expr, *args)
assert isinstance(node.expr, astNode.Name)
assert node.expr.name in self.ast.symdict
if node.expr.name not in self.ast.symdict:
raise AssertionError("attr target: %s" % node.expr.name)
node.obj = None
node.signed = False
obj = self.ast.symdict[node.expr.name]

2
myhdl/conversion/_misc.py
View File

@ -44,6 +44,8 @@ _error.SigMultipleDriven = "Signal has multiple drivers"
_error.UndefinedBitWidth = "Signal has undefined bit width"
_error.UndrivenSignal = "Signal is not driven"
_error.UnusedSignal = "Signal is driven but not used"
_error.UnusedPort = "Port is not used"
_error.OutputPortRead = "Output port is read internally"
_error.Requirement = "Requirement violation"
_error.UnboundLocal = "Local variable may be referenced before assignment"
_error.TypeMismatch = "Type mismatch with earlier assignment"

10
myhdl/conversion/_toVHDL.py
View File

@ -182,8 +182,16 @@ def _writeModuleHeader(f, intf):
r = _getRangeString(s)
p = _getTypeString(s)
if s._driven:
if s._read:
warnings.warn("%s: %s" % (_error.OutputPortRead, portname),
category=ToVHDLWarning
)
f.write("\n %s: out %s%s" % (portname, p, r))
else:
if not s._read:
warnings.warn("%s: %s" % (_error.UnusedPort, portname),
category=ToVHDLWarning
)
f.write("\n %s: in %s%s" % (portname, p, r))
f.write("\n );\n")
print >> f, "end entity %s;" % intf.name
@ -1712,7 +1720,7 @@ class _AnnotateTypesVisitor(_ConversionMixin):
def visitName(self, node):
node.vhd = node.vhdOri = inferVhdlObj(node.obj)
# visitAssName = visitName
def visitAssName(self, node):
node.obj = self.ast.vardict[node.name]

8
myhdl/conversion/_toVerilog.py
View File

@ -162,12 +162,20 @@ def _writeModuleHeader(f, intf):
r = _getRangeString(s)
p = _getSignString(s)
if s._driven:
if s._read:
warnings.warn("%s: %s" % (_error.OutputPortRead, portname),
category=ToVerilogWarning
)
print >> f, "output %s%s%s;" % (p, r, portname)
if s._driven == 'reg':
print >> f, "reg %s%s%s;" % (p, r, portname)
else:
print >> f, "wire %s%s%s;" % (p, r, portname)
else:
if not s._read:
warnings.warn("%s: %s" % (_error.UnusedPort, portname),
category=ToVerilogWarning
)
print >> f, "input %s%s%s;" % (p, r, portname)
print >> f

4
myhdl/conversion/_verify.py
View File

@ -40,8 +40,8 @@ def registerSimulator(name=None, hdl=None, analyze=None, elaborate=None, simulat
registerSimulator(name="GHDL",
hdl="VHDL",
analyze="ghdl -a --workdir=work pck_myhdl_%(version)s.vhd %(topname)s.vhd",
elaborate="ghdl -e --workdir=work %(topname)s",
simulate="ghdl -r %(topname)s")
elaborate="ghdl -e --workdir=work -o %(topname)s_ghdl %(topname)s",
simulate="ghdl -r %(topname)s_ghdl")
registerSimulator(name="icarus",
hdl="Verilog",