From cec118c8582f029b2c510faf487af0035970aeec Mon Sep 17 00:00:00 2001
From: jand <none@none>
Date: Tue, 13 Nov 2007 20:44:35 +0000
Subject: [PATCH] port usage warnings

---
 myhdl/conversion/_analyze.py   |  3 ++-
 myhdl/conversion/_misc.py      |  2 ++
 myhdl/conversion/_toVHDL.py    | 10 +++++++++-
 myhdl/conversion/_toVerilog.py |  8 ++++++++
 myhdl/conversion/_verify.py    |  4 ++--
 5 files changed, 23 insertions(+), 4 deletions(-)

diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py
index aaf3dbe9..6d2d9170 100644
--- a/myhdl/conversion/_analyze.py
+++ b/myhdl/conversion/_analyze.py
@@ -620,7 +620,8 @@ class _AnalyzeVisitor(_ConversionMixin):
     def visitGetattr(self, node, *args):
         self.visit(node.expr, *args)
         assert isinstance(node.expr, astNode.Name)
-        assert node.expr.name in self.ast.symdict
+        if node.expr.name not in self.ast.symdict:
+            raise AssertionError("attr target: %s" % node.expr.name)
         node.obj = None
         node.signed = False
         obj = self.ast.symdict[node.expr.name]
diff --git a/myhdl/conversion/_misc.py b/myhdl/conversion/_misc.py
index 6bbd18fb..d0bc88a1 100644
--- a/myhdl/conversion/_misc.py
+++ b/myhdl/conversion/_misc.py
@@ -44,6 +44,8 @@ _error.SigMultipleDriven = "Signal has multiple drivers"
 _error.UndefinedBitWidth = "Signal has undefined bit width"
 _error.UndrivenSignal = "Signal is not driven"
 _error.UnusedSignal = "Signal is driven but not used"
+_error.UnusedPort = "Port is not used"
+_error.OutputPortRead = "Output port is read internally"
 _error.Requirement = "Requirement violation"
 _error.UnboundLocal = "Local variable may be referenced before assignment"
 _error.TypeMismatch = "Type mismatch with earlier assignment"
diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
index a83d2d1e..2fb2b8e8 100644
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -182,8 +182,16 @@ def _writeModuleHeader(f, intf):
             r = _getRangeString(s)
             p = _getTypeString(s)
             if s._driven:
+                if s._read:
+                    warnings.warn("%s: %s" % (_error.OutputPortRead, portname),
+                                  category=ToVHDLWarning
+                                  )
                 f.write("\n        %s: out %s%s" % (portname, p, r))
             else:
+                if not s._read:
+                    warnings.warn("%s: %s" % (_error.UnusedPort, portname),
+                                  category=ToVHDLWarning
+                                  )
                 f.write("\n        %s: in %s%s" % (portname, p, r))
         f.write("\n    );\n")
     print >> f, "end entity %s;" % intf.name
@@ -1712,7 +1720,7 @@ class _AnnotateTypesVisitor(_ConversionMixin):
         
     def visitName(self, node):
         node.vhd = node.vhdOri = inferVhdlObj(node.obj)
- 
+  
     # visitAssName = visitName
     def visitAssName(self, node):
         node.obj = self.ast.vardict[node.name]
diff --git a/myhdl/conversion/_toVerilog.py b/myhdl/conversion/_toVerilog.py
index e9de82a4..105830e4 100644
--- a/myhdl/conversion/_toVerilog.py
+++ b/myhdl/conversion/_toVerilog.py
@@ -162,12 +162,20 @@ def _writeModuleHeader(f, intf):
         r = _getRangeString(s)
         p = _getSignString(s)
         if s._driven:
+            if s._read:
+                warnings.warn("%s: %s" % (_error.OutputPortRead, portname),
+                              category=ToVerilogWarning
+                              )
             print >> f, "output %s%s%s;" % (p, r, portname)
             if s._driven == 'reg':
                 print >> f, "reg %s%s%s;" % (p, r, portname)
             else:
                 print >> f, "wire %s%s%s;" % (p, r, portname)
         else:
+            if not s._read:
+                warnings.warn("%s: %s" % (_error.UnusedPort, portname),
+                              category=ToVerilogWarning
+                              )
             print >> f, "input %s%s%s;" % (p, r, portname)
     print >> f
 
diff --git a/myhdl/conversion/_verify.py b/myhdl/conversion/_verify.py
index 95ce5889..e5000856 100644
--- a/myhdl/conversion/_verify.py
+++ b/myhdl/conversion/_verify.py
@@ -40,8 +40,8 @@ def registerSimulator(name=None, hdl=None, analyze=None, elaborate=None, simulat
 registerSimulator(name="GHDL",
                   hdl="VHDL",
                   analyze="ghdl -a --workdir=work pck_myhdl_%(version)s.vhd %(topname)s.vhd",
-                  elaborate="ghdl -e --workdir=work %(topname)s",
-                  simulate="ghdl -r %(topname)s")
+                  elaborate="ghdl -e --workdir=work -o  %(topname)s_ghdl %(topname)s",
+                  simulate="ghdl -r %(topname)s_ghdl")
 
 registerSimulator(name="icarus",
                   hdl="Verilog",