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improving ast.Constant

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This commit is contained in:
Josy Boelen 2021-03-07 13:48:46 +01:00
parent 19066e0656
commit d01c4ee31b
2 changed files with 18 additions and 8 deletions
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3
myhdl/conversion/_toVHDL.py
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@ -1514,6 +1514,9 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
s = "to_signed(%s, %s)" % (obj, node.vhd.size)
else:
s = 'signed\'("%s")' % tobin(obj, node.vhd.size)
elif isinstance(obj, tuple): # Python3.9+ ast.Index replacement serves a tuple
print('toVHDL: getName:', node, n, obj)
s = n
elif isinstance(obj, _Signal):
s = str(obj)
ori = inferVhdlObj(obj)

23
myhdl/conversion/_toVerilog.py
View File

@ -758,10 +758,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
# self.write("// synthesis parallel_case full_case")
# self.writeline()
self.write("case (")
if sys.version_info >= (3, 9, 0): # Python 3.9+: no ast.Index wrapper
self.visit(node.value)
else:
self.visit(node.value.slice)
self.visit(node.value.slice)
self.write(")")
self.indent()
for i, n in enumerate(rom):
@ -859,6 +856,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
elif f is concat:
opening, closing = '{', '}'
elif f is delay:
print('toVerilog: visit_Call:', node, node.args[0])
self.visit(node.args[0])
return
elif hasattr(node, 'tree'):
@ -891,20 +889,27 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
self.write(")")
self.context = None
if sys.version_info >= (3, 8, 0):
if sys.version_info >= (3, 9, 0):
def visit_Constant(self, node):
if node.value in (True, False, None):
print('toVerilog: visit_Constant:', node.value, end=': ')
if node.value is None:
# NameConstant
print('NameConstant: None')
self.write(nameconstant_map[node.obj])
elif isinstance(node.value, bool):
print('NameConstant: bool')
self.write(nameconstant_map[node.obj])
elif isinstance(node.value, int):
# Num
print('Num')
if self.context == _context.PRINT:
self.write('"%s"' % node.value)
else:
self.write(self.IntRepr(node.value))
elif isinstance(node.value, str):
# Str
print('Str')
s = node.value
if self.context == _context.PRINT:
self.write('"%s"' % s)
@ -1132,8 +1137,8 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
s = "1'b%s" % int(obj)
elif isinstance(obj, int):
s = self.IntRepr(obj)
elif isinstance(obj, tuple): # Python3.9+ ast.Index serves a tuple
print('toVerilog', addSignBit, n, obj)
elif isinstance(obj, tuple): # Python3.9+ ast.Index replacement serves a tuple
print('toVerilog: getName:', node, addSignBit, n, obj)
s = n
# # print(ast.dump(ast.parse('l[i]', mode='eval')))
# # Expression(body=Subscript(value=Name(id='l', ctx=Load()), slice=Index(value=Name(id='i', ctx=Load())), ctx=Load()))
@ -1276,6 +1281,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
self.write("[")
# assert len(node.subs) == 1
if sys.version_info >= (3, 9, 0): # Python 3.9+: no ast.Index wrapper
print('toVerilog: accessIndex:', node, node.slice)
self.visit(node.slice)
else:
self.visit(node.slice.value)
@ -1329,6 +1335,7 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
if isinstance(yieldObj, delay):
self.write("# ")
self.context = _context.YIELD
print('toVerilog: visit_Yield: delay:', node, node.value)
self.visit(node.value)
self.context = _context.UNKNOWN
self.write(";")