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fix usage of x in integer_types,..

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This commit is contained in:
Keerthan Jaic 2015-02-06 07:46:59 -05:00
parent 79704daa15
commit d0dc39dc21
2 changed files with 5 additions and 4 deletions
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4
myhdl/conversion/_analyze.py
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@ -42,7 +42,7 @@ from myhdl.conversion._misc import (_error, _access, _kind,
from myhdl._extractHierarchy import _isMem, _getMemInfo, _UserCode
from myhdl._Signal import _Signal, _WaiterList
from myhdl._ShadowSignal import _ShadowSignal, _SliceSignal
from myhdl._util import _isTupleOfInts, _dedent, _makeAST
from myhdl._util import _isTupleOfInts, _dedent, _flatten, _makeAST
from myhdl._resolverefs import _AttrRefTransformer
from myhdl._compat import builtins, integer_types
@ -576,7 +576,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
node.obj = int(0) # XXX
elif f is bool:
node.obj = bool()
elif f in (integer_types, ord):
elif f in _flatten(integer_types, ord):
node.obj = int(-1)
## elif f in (posedge , negedge):
## node.obj = _EdgeDetector()

5
myhdl/conversion/_toVHDL.py
View File

@ -40,7 +40,6 @@ import string
import myhdl
from myhdl import *
from myhdl._compat import integer_types, class_types, StringIO
from myhdl import ToVHDLError, ToVHDLWarning
from myhdl._extractHierarchy import (_HierExtr, _isMem, _getMemInfo,
_UserVhdlCode, _userCodeMap)
@ -52,6 +51,8 @@ from myhdl.conversion._analyze import (_analyzeSigs, _analyzeGens, _analyzeTopFu
_Ram, _Rom, _enumTypeSet, _constDict, _extConstDict)
from myhdl._Signal import _Signal,_WaiterList
from myhdl.conversion._toVHDLPackage import _package
from myhdl._util import _flatten
from myhdl._compat import integer_types, class_types, StringIO
_version = myhdl.__version__.replace('.','')
@ -2053,7 +2054,7 @@ class _AnnotateTypesVisitor(ast.NodeVisitor, _ConversionMixin):
node.vhd = vhd_unsigned(s)
elif f is bool:
node.vhd = vhd_boolean()
elif f in (integer_types, ord):
elif f in _flatten(integer_types, ord):
node.vhd = vhd_int()
node.args[0].vhd = vhd_int()
elif f in (intbv, modbv):