mirror of
https://github.com/myhdl/myhdl.git
synced 2024-12-14 07:44:38 +08:00
Added index entry to intbv conversion documentation
This commit is contained in:
parent
e6ac4e8bef
commit
d3929bea20
@ -463,6 +463,8 @@ the type and bit width of the corresponding Verilog or VHDL object.
|
||||
:class:`intbv` objects
|
||||
----------------------
|
||||
|
||||
.. index:: single: intbv; conversion
|
||||
|
||||
Type :class:`intbv` is likely to be the workhorse for synthesizable
|
||||
modeling in MyHDL. An :class:`intbv` instance behaves like a (mutable)
|
||||
integer whose individual bits can be accessed and modified. Also, it
|
||||
|
Loading…
x
Reference in New Issue
Block a user