Refactored set_inheritance code into the _util module

Fixed the VPI tests for Windows

cosimulation/modelsim-win/Makefile

@@ -0,0 +1,21 @@
+INCS := C:\\modeltech64_10.4\\include
+LIB_PATH := C:\\modeltech64_10.4\\win64
+
+ifneq ($(filter cl%,$(CC)),)
+	CFLAGS := /LD /I$(INCS)
+	LIBFLAGS := $(LIB_PATH)\\mtipli.lib
+else
+	CFLAGS := -static -g -I$(INCS) -o myhdl_vpi.dll
+	LIBFLAGS := -L$(LIB_PATH) -lmtipli
+endif
+
+all: myhdl_vpi.dll
+
+myhdl_vpi.dll: myhdl_vpi.c
+	$(CC) $(CFLAGS) $< $(LIBFLAGS)
+
+clean:
+	@del /q myhdl_vpi.dll || rm -rf myhdl_vpi.dll 2>&1> /dev/null ||:
+	@del /q myhdl_vpi.lib || rm -rf myhdl_vpi.lib 2>&1> /dev/null ||:
+	@del /q myhdl_vpi.exp || rm -rf myhdl_vpi.exp 2>&1> /dev/null ||:
+	@del /q myhdl_vpi.obj || rm -rf myhdl_vpi.obj 2>&1> /dev/null ||:

cosimulation/modelsim-win/myhdl_vpi.c

@@ -163,7 +163,7 @@ static PLI_INT32 from_myhdl_calltf(PLI_BYTE8 *user_data)
 
   n = write_pipe(buf, strlen(buf));
 
-  if ((n = read_pipe(buf, MAXLINE)) == 0) {
+  if ((n = read_pipe(buf, MAXLINE)) <= 0) {
     vpi_printf("Info: MyHDL simulator down\n");
     vpi_control(vpiFinish, 1);  /* abort simulation */
     return(0);
@@ -242,7 +242,7 @@ static PLI_INT32 to_myhdl_calltf(PLI_BYTE8 *user_data)
 
   n = write_pipe(buf, strlen(buf));
 
-  if ((n = read_pipe(buf, MAXLINE)) == 0) {
+  if ((n = read_pipe(buf, MAXLINE)) <= 0) {
     vpi_printf("ABORT from $to_myhdl\n");
     vpi_control(vpiFinish, 1);  /* abort simulation */
     return(0);
@@ -300,7 +300,7 @@ static PLI_INT32 readonly_callback(p_cb_data cb_data)
     start_flag = 0;
     n = write_pipe("START", 5);
     // vpi_printf("INFO: RO cb at start-up\n");
-    if ((n = read_pipe(buf, MAXLINE)) == 0) {
+    if ((n = read_pipe(buf, MAXLINE)) <= 0) {
       vpi_printf("ABORT from RO cb at start-up\n");
       vpi_control(vpiFinish, 1);  /* abort simulation */
     }
@@ -337,7 +337,7 @@ static PLI_INT32 readonly_callback(p_cb_data cb_data)
   //vpi_free_object(net_iter);
 
   n = write_pipe(buf, strlen(buf));
-  if ((n = read_pipe(buf, MAXLINE)) == 0) {
+  if ((n = read_pipe(buf, MAXLINE)) <= 0) {
     // vpi_printf("ABORT from RO cb\n");
     vpi_control(vpiFinish, 1);  /* abort simulation */
     return(0);

cosimulation/modelsim-win/test/bin2gray.py

@@ -2,12 +2,10 @@ import os
 
 from myhdl import Cosimulation
 
-cmd = 'vsim -c -quiet -pli ../myhdl_vpi.so -do cosim.do dut_bin2gray'
+cmd = 'vsim -c -quiet -pli ../myhdl_vpi.dll -do cosim.do dut_bin2gray'
-       
+
 def bin2gray(B, G, width):
     os.system('vlog -quiet +define+width=%s ../../test/verilog/bin2gray.v' % (width))
-    os.system('vlog -quiet +define+width=%s ../../test/verilog/dut_bin2gray.v' % (width)) 
+    os.system('vlog -quiet +define+width=%s ../../test/verilog/dut_bin2gray.v' % (width))
 
     return Cosimulation(cmd, B=B, G=G)
-               
-

cosimulation/modelsim-win/test/dff.py

@@ -2,11 +2,10 @@ import os
 
 from myhdl import Cosimulation
 
-cmd = 'vsim -c -quiet -pli ../myhdl_vpi.so -do cosim.do dut_dff'
+cmd = 'vsim -c -quiet -pli ../myhdl_vpi.dll -do cosim.do dut_dff'
-      
+
 def dff(q, d, clk, reset):
     os.system('vlog -quiet ../../test/verilog/dff.v')
-    os.system('vlog -quiet ../../test/verilog/dut_dff.v') 
+    os.system('vlog -quiet ../../test/verilog/dut_dff.v')
 
     return Cosimulation(cmd, **locals())
-               

cosimulation/modelsim-win/test/dff_clkout.py

@@ -1,13 +1,11 @@
 import os
-import os.path as path
 
 from myhdl import Cosimulation
 
-cmd = 'vsim -c -quiet -pli ../myhdl_vpi.so -do cosim.do dut_dff_clkout'
+cmd = 'vsim -c -quiet -pli ../myhdl_vpi.dll -do cosim.do dut_dff_clkout'
-      
+
 def dff_clkout(clkout, q, d, clk, reset):
     os.system('vlog -quiet ../../test/verilog/dff_clkout.v')
     os.system('vlog -quiet ../../test/verilog/dut_dff_clkout.v')
-    
+
     return Cosimulation(cmd, **locals())
-               

cosimulation/modelsim-win/test/inc.py

@@ -2,11 +2,10 @@ import os
 
 from myhdl import Cosimulation
 
-cmd = 'vsim -c -quiet -pli ../myhdl_vpi.so -do cosim.do dut_inc'
+cmd = 'vsim -c -quiet -pli ../myhdl_vpi.dll -do cosim.do dut_inc'
 
 def inc(count, enable, clock, reset, n):
     os.system('vlog -quiet +define+n=%s ../../test/verilog/inc.v' % (n))
-    os.system('vlog -quiet +define+n=%s ../../test/verilog/dut_inc.v' % (n)) 
+    os.system('vlog -quiet +define+n=%s ../../test/verilog/dut_inc.v' % (n))
 
     return Cosimulation(cmd, **locals())
-               

cosimulation/modelsim-win/test/test_all.py

@@ -41,7 +41,7 @@ def suite():
 def main():
     unittest.main(defaultTest='suite',
                   testRunner=unittest.TextTestRunner(verbosity=2))
-    
+
 
 if __name__ == '__main__':
     main()

myhdl/_Cosimulation.py

@@ -24,15 +24,15 @@ import sys
 import os
 import shlex
 import subprocess
-if sys.platform == "win32":
-    import msvcrt
 
 from myhdl._intbv import intbv
 from myhdl import _simulator, CosimulationError
 from myhdl._compat import string_types, to_bytes, to_str
+from myhdl._util import _setInheritable
 
 _MAXLINE = 4096
 
+
 class _error:
     pass
 _error.MultipleCosim = "Only a single cosimulator allowed"
@@ -43,6 +43,7 @@ _error.NoCommunication = "No signals communicating to myhdl"
 _error.SimulationEnd = "Premature simulation end"
 _error.OSError = "OSError"
 
+
 class Cosimulation(object):
 
     """ Cosimulation class. """
@@ -58,17 +59,13 @@ class Cosimulation(object):
         rt, wt = os.pipe()
         rf, wf = os.pipe()
 
-        # Support for python 3.4 non-inheritable pipes
+        # Disable inheritance for ends that we don't want the child to have
-        # On < 3.4 Windows still has non-inheritable pipes, but < 3.4 support
+        _setInheritable(rt, False)
-        # was dropped in [#38](https://github.com/jandecaluwe/myhdl/issues/38)
+        _setInheritable(wf, False)
-        if hasattr(os, 'set_inheritable'):
-            # Disable inheritance for ends that we don't want the child to have
-            os.set_inheritable(rt, False)
-            os.set_inheritable(wf, False)
 
-            # Enable inheritance for child ends
+        # Enable inheritance for child ends
-            os.set_inheritable(wt, True)
+        _setInheritable(wt, True)
-            os.set_inheritable(rf, True)
+        _setInheritable(rf, True)
 
         self._rt = rt
         self._wf = wf
@@ -91,6 +88,7 @@ class Cosimulation(object):
             env['MYHDL_TO_PIPE'] = str(wt)
             env['MYHDL_FROM_PIPE'] = str(rf)
         else:
+            import msvcrt
             env['MYHDL_TO_PIPE'] = str(msvcrt.get_osfhandle(wt))
             env['MYHDL_FROM_PIPE'] = str(msvcrt.get_osfhandle(rf))
 

myhdl/_util.py

@@ -23,15 +23,16 @@
 from __future__ import absolute_import
 from __future__ import print_function
 
-
 import ast
 import sys
+import os
 import inspect
 
 from tokenize import generate_tokens, untokenize, INDENT
 
 from myhdl._compat import integer_types, StringIO
 
+
 def _printExcInfo():
     kind, value = sys.exc_info()[:2]
     msg = str(kind)
@@ -91,3 +92,29 @@ def _genfunc(gen):
     else:
         func = gen.genfunc
     return func
+
+if hasattr(os, 'set_inheritable'):
+    _setInheritable = os.set_inheritable
+else:
+    def _setInheritable(fd, inheritable):
+        if sys.platform == "win32":
+            import msvcrt
+            import ctypes.windll.kernel32 as kernel32
+
+            HANDLE_FLAG_INHERIT = 1
+
+            if kernel32.SetHandleInformation(msvcrt.get_osfhandle(fd),
+                                             HANDLE_FLAG_INHERIT,
+                                             1 if inheritable else 0) == 0:
+                raise IOError("Failed on HANDLE_FLAG_INHERIT")
+        else:
+            import fcntl
+
+            fd_flags = fcntl.fcntl(fd, fcntl.F_GETFD)
+
+            if inheritable:
+                fd_flags &= ~fcntl.FD_CLOEXEC
+            else:
+                fd_flags |= fcntl.FD_CLOEXEC
+
+            fcntl.fcntl(fd, fcntl.F_SETFD, fd_flags)