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https://github.com/myhdl/myhdl.git
synced 2025-01-24 21:52:56 +08:00
Refactored set_inheritance code into the _util module
Fixed the VPI tests for Windows
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commit
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21
cosimulation/modelsim-win/Makefile
Normal file
21
cosimulation/modelsim-win/Makefile
Normal file
@ -0,0 +1,21 @@
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INCS := C:\\modeltech64_10.4\\include
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LIB_PATH := C:\\modeltech64_10.4\\win64
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ifneq ($(filter cl%,$(CC)),)
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CFLAGS := /LD /I$(INCS)
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LIBFLAGS := $(LIB_PATH)\\mtipli.lib
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else
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CFLAGS := -static -g -I$(INCS) -o myhdl_vpi.dll
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LIBFLAGS := -L$(LIB_PATH) -lmtipli
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endif
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all: myhdl_vpi.dll
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myhdl_vpi.dll: myhdl_vpi.c
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$(CC) $(CFLAGS) $< $(LIBFLAGS)
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clean:
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@del /q myhdl_vpi.dll || rm -rf myhdl_vpi.dll 2>&1> /dev/null ||:
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@del /q myhdl_vpi.lib || rm -rf myhdl_vpi.lib 2>&1> /dev/null ||:
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@del /q myhdl_vpi.exp || rm -rf myhdl_vpi.exp 2>&1> /dev/null ||:
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@del /q myhdl_vpi.obj || rm -rf myhdl_vpi.obj 2>&1> /dev/null ||:
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@ -163,7 +163,7 @@ static PLI_INT32 from_myhdl_calltf(PLI_BYTE8 *user_data)
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n = write_pipe(buf, strlen(buf));
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if ((n = read_pipe(buf, MAXLINE)) == 0) {
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if ((n = read_pipe(buf, MAXLINE)) <= 0) {
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vpi_printf("Info: MyHDL simulator down\n");
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vpi_control(vpiFinish, 1); /* abort simulation */
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return(0);
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@ -242,7 +242,7 @@ static PLI_INT32 to_myhdl_calltf(PLI_BYTE8 *user_data)
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n = write_pipe(buf, strlen(buf));
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if ((n = read_pipe(buf, MAXLINE)) == 0) {
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if ((n = read_pipe(buf, MAXLINE)) <= 0) {
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vpi_printf("ABORT from $to_myhdl\n");
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vpi_control(vpiFinish, 1); /* abort simulation */
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return(0);
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@ -300,7 +300,7 @@ static PLI_INT32 readonly_callback(p_cb_data cb_data)
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start_flag = 0;
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n = write_pipe("START", 5);
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// vpi_printf("INFO: RO cb at start-up\n");
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if ((n = read_pipe(buf, MAXLINE)) == 0) {
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if ((n = read_pipe(buf, MAXLINE)) <= 0) {
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vpi_printf("ABORT from RO cb at start-up\n");
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vpi_control(vpiFinish, 1); /* abort simulation */
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}
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@ -337,7 +337,7 @@ static PLI_INT32 readonly_callback(p_cb_data cb_data)
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//vpi_free_object(net_iter);
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n = write_pipe(buf, strlen(buf));
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if ((n = read_pipe(buf, MAXLINE)) == 0) {
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if ((n = read_pipe(buf, MAXLINE)) <= 0) {
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// vpi_printf("ABORT from RO cb\n");
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vpi_control(vpiFinish, 1); /* abort simulation */
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return(0);
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@ -2,12 +2,10 @@ import os
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from myhdl import Cosimulation
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cmd = 'vsim -c -quiet -pli ../myhdl_vpi.so -do cosim.do dut_bin2gray'
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cmd = 'vsim -c -quiet -pli ../myhdl_vpi.dll -do cosim.do dut_bin2gray'
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def bin2gray(B, G, width):
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os.system('vlog -quiet +define+width=%s ../../test/verilog/bin2gray.v' % (width))
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os.system('vlog -quiet +define+width=%s ../../test/verilog/dut_bin2gray.v' % (width))
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return Cosimulation(cmd, B=B, G=G)
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@ -2,11 +2,10 @@ import os
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from myhdl import Cosimulation
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cmd = 'vsim -c -quiet -pli ../myhdl_vpi.so -do cosim.do dut_dff'
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cmd = 'vsim -c -quiet -pli ../myhdl_vpi.dll -do cosim.do dut_dff'
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def dff(q, d, clk, reset):
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os.system('vlog -quiet ../../test/verilog/dff.v')
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os.system('vlog -quiet ../../test/verilog/dut_dff.v')
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return Cosimulation(cmd, **locals())
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@ -1,13 +1,11 @@
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import os
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import os.path as path
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from myhdl import Cosimulation
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cmd = 'vsim -c -quiet -pli ../myhdl_vpi.so -do cosim.do dut_dff_clkout'
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cmd = 'vsim -c -quiet -pli ../myhdl_vpi.dll -do cosim.do dut_dff_clkout'
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def dff_clkout(clkout, q, d, clk, reset):
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os.system('vlog -quiet ../../test/verilog/dff_clkout.v')
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os.system('vlog -quiet ../../test/verilog/dut_dff_clkout.v')
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return Cosimulation(cmd, **locals())
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@ -2,11 +2,10 @@ import os
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from myhdl import Cosimulation
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cmd = 'vsim -c -quiet -pli ../myhdl_vpi.so -do cosim.do dut_inc'
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cmd = 'vsim -c -quiet -pli ../myhdl_vpi.dll -do cosim.do dut_inc'
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def inc(count, enable, clock, reset, n):
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os.system('vlog -quiet +define+n=%s ../../test/verilog/inc.v' % (n))
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os.system('vlog -quiet +define+n=%s ../../test/verilog/dut_inc.v' % (n))
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return Cosimulation(cmd, **locals())
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@ -24,15 +24,15 @@ import sys
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import os
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import shlex
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import subprocess
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if sys.platform == "win32":
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import msvcrt
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from myhdl._intbv import intbv
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from myhdl import _simulator, CosimulationError
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from myhdl._compat import string_types, to_bytes, to_str
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from myhdl._util import _setInheritable
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_MAXLINE = 4096
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class _error:
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pass
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_error.MultipleCosim = "Only a single cosimulator allowed"
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@ -43,6 +43,7 @@ _error.NoCommunication = "No signals communicating to myhdl"
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_error.SimulationEnd = "Premature simulation end"
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_error.OSError = "OSError"
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class Cosimulation(object):
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""" Cosimulation class. """
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@ -58,17 +59,13 @@ class Cosimulation(object):
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rt, wt = os.pipe()
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rf, wf = os.pipe()
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# Support for python 3.4 non-inheritable pipes
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# On < 3.4 Windows still has non-inheritable pipes, but < 3.4 support
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# was dropped in [#38](https://github.com/jandecaluwe/myhdl/issues/38)
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if hasattr(os, 'set_inheritable'):
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# Disable inheritance for ends that we don't want the child to have
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os.set_inheritable(rt, False)
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os.set_inheritable(wf, False)
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_setInheritable(rt, False)
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_setInheritable(wf, False)
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# Enable inheritance for child ends
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os.set_inheritable(wt, True)
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os.set_inheritable(rf, True)
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_setInheritable(wt, True)
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_setInheritable(rf, True)
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self._rt = rt
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self._wf = wf
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@ -91,6 +88,7 @@ class Cosimulation(object):
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env['MYHDL_TO_PIPE'] = str(wt)
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env['MYHDL_FROM_PIPE'] = str(rf)
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else:
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import msvcrt
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env['MYHDL_TO_PIPE'] = str(msvcrt.get_osfhandle(wt))
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env['MYHDL_FROM_PIPE'] = str(msvcrt.get_osfhandle(rf))
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@ -23,15 +23,16 @@
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from __future__ import absolute_import
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from __future__ import print_function
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import ast
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import sys
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import os
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import inspect
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from tokenize import generate_tokens, untokenize, INDENT
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from myhdl._compat import integer_types, StringIO
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def _printExcInfo():
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kind, value = sys.exc_info()[:2]
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msg = str(kind)
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@ -91,3 +92,29 @@ def _genfunc(gen):
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else:
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func = gen.genfunc
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return func
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if hasattr(os, 'set_inheritable'):
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_setInheritable = os.set_inheritable
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else:
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def _setInheritable(fd, inheritable):
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if sys.platform == "win32":
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import msvcrt
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import ctypes.windll.kernel32 as kernel32
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HANDLE_FLAG_INHERIT = 1
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if kernel32.SetHandleInformation(msvcrt.get_osfhandle(fd),
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HANDLE_FLAG_INHERIT,
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1 if inheritable else 0) == 0:
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raise IOError("Failed on HANDLE_FLAG_INHERIT")
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else:
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import fcntl
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fd_flags = fcntl.fcntl(fd, fcntl.F_GETFD)
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if inheritable:
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fd_flags &= ~fcntl.FD_CLOEXEC
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else:
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fd_flags |= fcntl.FD_CLOEXEC
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fcntl.fcntl(fd, fcntl.F_SETFD, fd_flags)
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