diff --git a/example/manual/gray_inc_reg.py b/example/manual/gray_inc_reg.py index 0b6000c2..6869a211 100644 --- a/example/manual/gray_inc_reg.py +++ b/example/manual/gray_inc_reg.py @@ -8,7 +8,6 @@ def gray_inc_reg(graycnt, enable, clock, reset, width): graycnt_comb = Signal(modbv(0)[width:]) gray_inc_0 = gray_inc(graycnt_comb, enable, clock, reset, width) - gray_inc_0.name = "gray_inc_0" @always_seq(clock.posedge, reset=reset) def reg_0(): diff --git a/example/manual/gray_inc_reg.v b/example/manual/gray_inc_reg.v index 938502e3..6f2c72e2 100644 --- a/example/manual/gray_inc_reg.v +++ b/example/manual/gray_inc_reg.v @@ -1,6 +1,6 @@ // File: gray_inc_reg.v // Generated by MyHDL 1.0dev -// Date: Mon May 23 18:06:58 2016 +// Date: Thu Jun 23 19:06:43 2016 `timescale 1ns/10ps @@ -20,23 +20,24 @@ input clock; input reset; wire [7:0] graycnt_comb; -reg [7:0] gray_inc_0_bincnt; +reg [7:0] gray_inc_1_bincnt; -always @(posedge clock, negedge reset) begin: GRAY_INC_REG_GRAY_INC_0_INC_0_SEQ + +always @(posedge clock, negedge reset) begin: GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ if (reset == 0) begin - gray_inc_0_bincnt <= 0; + gray_inc_1_bincnt <= 0; end else begin if (enable) begin - gray_inc_0_bincnt <= (gray_inc_0_bincnt + 1); + gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1); end end end -assign graycnt_comb = ((gray_inc_0_bincnt >>> 1) ^ gray_inc_0_bincnt); +assign graycnt_comb = ((gray_inc_1_bincnt >>> 1) ^ gray_inc_1_bincnt); always @(posedge clock, negedge reset) begin: GRAY_INC_REG_REG_0 diff --git a/example/manual/gray_inc_reg.vhd b/example/manual/gray_inc_reg.vhd index 20f0402f..0a0a418b 100644 --- a/example/manual/gray_inc_reg.vhd +++ b/example/manual/gray_inc_reg.vhd @@ -1,6 +1,6 @@ -- File: gray_inc_reg.vhd -- Generated by MyHDL 1.0dev --- Date: Mon May 23 18:06:58 2016 +-- Date: Thu Jun 23 19:06:43 2016 library IEEE; @@ -24,26 +24,26 @@ architecture MyHDL of gray_inc_reg is signal graycnt_comb: unsigned(7 downto 0); -signal gray_inc_0_bincnt: unsigned(7 downto 0); +signal gray_inc_1_bincnt: unsigned(7 downto 0); begin -GRAY_INC_REG_GRAY_INC_0_INC_1_SEQ: process (clock, reset) is +GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ: process (clock, reset) is begin if (reset = '0') then - gray_inc_0_bincnt <= to_unsigned(0, 8); + gray_inc_1_bincnt <= to_unsigned(0, 8); elsif rising_edge(clock) then if bool(enable) then - gray_inc_0_bincnt <= (gray_inc_0_bincnt + 1); + gray_inc_1_bincnt <= (gray_inc_1_bincnt + 1); end if; end if; -end process GRAY_INC_REG_GRAY_INC_0_INC_1_SEQ; +end process GRAY_INC_REG_GRAY_INC_1_INC_1_SEQ; -graycnt_comb <= (shift_right(gray_inc_0_bincnt, 1) xor gray_inc_0_bincnt); +graycnt_comb <= (shift_right(gray_inc_1_bincnt, 1) xor gray_inc_1_bincnt); GRAY_INC_REG_REG_0: process (clock, reset) is begin diff --git a/example/manual/pck_myhdl_10.vhd b/example/manual/pck_myhdl_10.vhd index cabbc7ce..4dcb19a7 100644 --- a/example/manual/pck_myhdl_10.vhd +++ b/example/manual/pck_myhdl_10.vhd @@ -1,6 +1,6 @@ -- File: pck_myhdl_10.vhd -- Generated by MyHDL 1.0dev --- Date: Mon May 23 18:06:58 2016 +-- Date: Thu Jun 23 19:06:43 2016 library ieee; diff --git a/myhdl/_Signal.py b/myhdl/_Signal.py index 061cca70..c1d31364 100644 --- a/myhdl/_Signal.py +++ b/myhdl/_Signal.py @@ -137,8 +137,8 @@ class _Signal(object): self._val = deepcopy(val) self._next = deepcopy(val) self._min = self._max = None - self._name = self._read = self._driven = None - self._used = False + self._name = self._driven = None + self._read = self._used = False self._inList = False self._nrbits = 0 self._numeric = True @@ -183,7 +183,8 @@ class _Signal(object): del self._negedgeWaiters[:] self._val = deepcopy(self._init) self._next = deepcopy(self._init) - self._name = self._read = self._driven = None + self._name = self._driven = None + self._read = False # dont clear self._used self._numeric = True for s in self._slicesigs: s._clear() diff --git a/myhdl/_block.py b/myhdl/_block.py index 1dae170c..8c8143ca 100644 --- a/myhdl/_block.py +++ b/myhdl/_block.py @@ -92,14 +92,13 @@ def _getCallInfo(): class _bound_function_wrapper(object): def __init__(self, bound_func, srcfile, srcline): - self.srcfile = srcfile self.srcline = srcline - self.bound_func = bound_func functools.update_wrapper(self, bound_func) - self.calls = 0 + # register the block + myhdl._simulator._blocks.append(self) def __call__(self, *args, **kwargs): self.calls += 1 @@ -110,19 +109,17 @@ class block(object): def __init__(self, func): self.srcfile = inspect.getsourcefile(func) self.srcline = inspect.getsourcelines(func)[0] - self.func = func functools.update_wrapper(self, func) - self.calls = 0 + # register the block + myhdl._simulator._blocks.append(self) def __get__(self, instance, owner): - bound_func = self.func.__get__(instance, owner) return _bound_function_wrapper(bound_func, self.srcfile, self.srcline) def __call__(self, *args, **kwargs): - self.calls += 1 return _Block(self.func, self, self.srcfile, self.srcline, *args, **kwargs) @@ -155,7 +152,7 @@ class _Block(object): self.symdict = None self.sigdict = {} self.memdict = {} - self.name = self.__name__ = func.__name__ + '_' + str(calls - 1) + self.name = self.__name__ = func.__name__ + '_' + str(calls) # flatten, but keep BlockInstance objects self.subs = _flatten(func(*args, **kwargs)) @@ -222,10 +219,22 @@ class _Block(object): # Public methods # The puropse now is to define the API, optimizations later + def _clear(self): + """ Clear a number of 'global' attributes. + This is a workaround function for cleaning up before converts. + """ + # workaround: elaborate again for the side effect on signal attibutes + self.func(*self.args, **self.kwargs) + # reset number of calls in all blocks + for b in myhdl._simulator._blocks: + b.calls = 0 + def verify_convert(self): + self._clear() return myhdl.conversion.verify(self) def analyze_convert(self): + self._clear() return myhdl.conversion.analyze(self) def convert(self, hdl='Verilog', **kwargs): @@ -243,6 +252,9 @@ class _Block(object): testbench should be created. Defaults to True. timescale(Optional[str]): Verilog only. Defaults to '1ns/10ps' """ + + self._clear() + if hdl.lower() == 'vhdl': converter = myhdl.conversion._toVHDL.toVHDL elif hdl.lower() == 'verilog': diff --git a/myhdl/_simulator.py b/myhdl/_simulator.py index 9e3013c9..ba3b93f4 100644 --- a/myhdl/_simulator.py +++ b/myhdl/_simulator.py @@ -26,6 +26,7 @@ now -- function that returns the current simulation time _signals = [] +_blocks = [] _siglist = [] _futureEvents = [] _time = 0