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refactored

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This commit is contained in:
jand 2003-10-30 17:50:07 +00:00
parent cb1f322daa
commit d5830ebbc1
4 changed files with 59 additions and 52 deletions
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10
myhdl/test/toVerilog/test_bin2gray.py
View File

@ -18,14 +18,14 @@ def bin2gray(B, G, width):
for i in range(width): for i in range(width):
G.next[i] = B[i+1] ^ B[i] G.next[i] = B[i+1] ^ B[i]
objfile = "bin2gray.o"
analyze_cmd = "iverilog -o bin2gray bin2gray_1.v tb_bin2gray_1.v" analyze_cmd = "iverilog -o %s bin2gray_1.v tb_bin2gray_1.v" % objfile
simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi bin2gray" simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi %s" % objfile
def bin2gray_v(B, G): def bin2gray_v(B, G):
if path.exists("bin2gray"): if path.exists(objfile):
os.remove("bin2gray") os.remove(objfile)
os.system(analyze_cmd) os.system(analyze_cmd)
return Cosimulation(simulate_cmd, **locals()) return Cosimulation(simulate_cmd, **locals())

12
myhdl/test/toVerilog/test_fsm.py
View File

@ -10,6 +10,8 @@ ACTIVE_LOW = 0
FRAME_SIZE = 8 FRAME_SIZE = 8
t_State = enum('SEARCH', 'CONFIRM', 'SYNC') t_State = enum('SEARCH', 'CONFIRM', 'SYNC')
def FramerCtrl(SOF, state, syncFlag, clk, reset_n): def FramerCtrl(SOF, state, syncFlag, clk, reset_n):
""" Framing control FSM. """ Framing control FSM.
@ -61,14 +63,14 @@ def FramerCtrl(SOF, state, syncFlag, clk, reset_n):
FSM_1 = FSM() FSM_1 = FSM()
return FSM_1 return FSM_1
objfile = "framerctrl.o"
analyze_cmd = "iverilog -o framerctrl framerctrl.v tb_framerctrl.v" analyze_cmd = "iverilog -o %s framerctrl.v tb_framerctrl.v" % objfile
simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi framerctrl" simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi %s" % objfile
def FramerCtrl_v(SOF, state, syncFlag, clk, reset_n): def FramerCtrl_v(SOF, state, syncFlag, clk, reset_n):
if path.exists("framectrl"): if path.exists(objfile):
os.remove("framectrl") os.remove(objfile)
os.system(analyze_cmd) os.system(analyze_cmd)
return Cosimulation(simulate_cmd, **locals()) return Cosimulation(simulate_cmd, **locals())

10
myhdl/test/toVerilog/test_inc.py
View File

@ -27,15 +27,15 @@ def inc(count, enable, clock, reset, n):
if enable: if enable:
count.next = (count + 1) % n count.next = (count + 1) % n
objfile = "inc_1.o"
analyze_cmd = "iverilog -o inc_1 inc_1.v tb_inc_1.v" analyze_cmd = "iverilog -o %s inc_1.v tb_inc_1.v" % objfile
simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi inc_1" simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi %s" % objfile
def top(count, enable, clock, reset, n, arch="myhdl"): def top(count, enable, clock, reset, n, arch="myhdl"):
if arch == "verilog": if arch == "verilog":
if path.exists("inc_1"): if path.exists(objfile):
os.remove("inc_1") os.remove(objfile)
os.system(analyze_cmd) os.system(analyze_cmd)
return Cosimulation(simulate_cmd, **locals()) return Cosimulation(simulate_cmd, **locals())
else: else:

79
myhdl/test/toVerilog/test_ops.py
View File

@ -8,6 +8,7 @@ random.seed(2)
from myhdl import * from myhdl import *
def binaryOps( def binaryOps(
Bitand, Bitand,
Bitor, Bitor,
@ -28,7 +29,7 @@ def binaryOps(
And, And,
Or, Or,
left, right): left, right):
while 1: while 1:
yield left, right yield left, right
Bitand.next = left & right Bitand.next = left & right
Bitor.next = left | right Bitor.next = left | right
@ -36,7 +37,7 @@ def binaryOps(
if right != 0: if right != 0:
FloorDiv.next = left // right FloorDiv.next = left // right
if left < 256 and right < 40: if left < 256 and right < 40:
LeftShift.next = left << right LeftShift.next = left << right
if right != 0: if right != 0:
Mod.next = left % right Mod.next = left % right
Mul.next = left * right Mul.next = left * right
@ -52,9 +53,9 @@ def binaryOps(
GE.next = left >= right GE.next = left >= right
And.next = bool(left and right) And.next = bool(left and right)
Or.next = bool(left or right) Or.next = bool(left or right)
def binaryOps_v( def binaryOps_v(
Bitand, Bitand,
Bitor, Bitor,
@ -75,11 +76,12 @@ def binaryOps_v(
And, And,
Or, Or,
left, right): left, right):
analyze_cmd = "iverilog -o binops binops.v tb_binops.v" objfile = "binops.o"
simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi binops" analyze_cmd = "iverilog -o %s binops.v tb_binops.v" % objfile
if path.exists("binops"): simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi %s" % objfile
os.remove("binops") if path.exists(objfile):
os.system(analyze_cmd) os.remove(objfile)
os.system(analyze_cmd)
return Cosimulation(simulate_cmd, **locals()) return Cosimulation(simulate_cmd, **locals())
class TestBinaryOps(TestCase): class TestBinaryOps(TestCase):
@ -116,7 +118,7 @@ class TestBinaryOps(TestCase):
EQ_v, NE_v, LT_v, GT_v, LE_v, GE_v = [Signal(bool()) for i in range(6)] EQ_v, NE_v, LT_v, GT_v, LE_v, GE_v = [Signal(bool()) for i in range(6)]
And, Or = [Signal(bool()) for i in range(2)] And, Or = [Signal(bool()) for i in range(2)]
And_v, Or_v, = [Signal(bool()) for i in range(2)] And_v, Or_v, = [Signal(bool()) for i in range(2)]
binops = toVerilog(binaryOps, binops = toVerilog(binaryOps,
Bitand, Bitand,
Bitor, Bitor,
@ -199,11 +201,11 @@ class TestBinaryOps(TestCase):
return binops, binops_v, stimulus(), check() return binops, binops_v, stimulus(), check()
def testBinaryOps(self): def testBinaryOps(self):
for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)): for m, n in ((4, 4,), (5, 3), (2, 6), (8, 7)):
sim = self.binaryBench(m, n) sim = self.binaryBench(m, n)
Simulation(sim).run() Simulation(sim).run()
def multiOps( def multiOps(
@ -213,15 +215,15 @@ def multiOps(
And, And,
Or, Or,
argm, argn, argp): argm, argn, argp):
while 1: while 1:
yield argm, argn, argp yield argm, argn, argp
Bitand.next = argm & argn & argp Bitand.next = argm & argn & argp
Bitor.next = argm | argn | argp Bitor.next = argm | argn | argp
Bitxor.next = argm ^ argn ^ argp Bitxor.next = argm ^ argn ^ argp
And.next = bool(argm and argn and argp) And.next = bool(argm and argn and argp)
Or.next = bool(argm and argn and argp) Or.next = bool(argm and argn and argp)
def multiOps_v( def multiOps_v(
Bitand, Bitand,
Bitor, Bitor,
@ -229,10 +231,12 @@ def multiOps_v(
And, And,
Or, Or,
argm, argn, argp): argm, argn, argp):
analyze_cmd = "iverilog -o multiops multiops.v tb_multiops.v"
simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi multiops" objfile = "multiops.o"
if path.exists("multiops"): analyze_cmd = "iverilog -o %s multiops.v tb_multiops.v" % objfile
os.remove("multiops") simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi %s" % objfile
if path.exists(objfile):
os.remove(objfile)
os.system(analyze_cmd) os.system(analyze_cmd)
return Cosimulation(simulate_cmd, **locals()) return Cosimulation(simulate_cmd, **locals())
@ -255,7 +259,7 @@ class TestMultiOps(TestCase):
Bitxor_v = Signal(intbv(0)[max(m, n, p):]) Bitxor_v = Signal(intbv(0)[max(m, n, p):])
And, Or = [Signal(bool()) for i in range(2)] And, Or = [Signal(bool()) for i in range(2)]
And_v, Or_v, = [Signal(bool()) for i in range(2)] And_v, Or_v, = [Signal(bool()) for i in range(2)]
multiops = toVerilog(multiOps, multiops = toVerilog(multiOps,
Bitand, Bitand,
Bitor, Bitor,
@ -315,23 +319,24 @@ def unaryOps(
Not, Not,
Invert, Invert,
arg): arg):
while 1: while 1:
yield arg yield arg
Not.next = not arg Not.next = not arg
Invert.next = ~arg Invert.next = ~arg
def unaryOps_v( def unaryOps_v(
Not, Not,
Invert, Invert,
arg): arg):
analyze_cmd = "iverilog -o unaryops unaryops.v tb_unaryops.v" objfile = "unaryops.o"
simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi unaryops" analyze_cmd = "iverilog -o %s unaryops.v tb_unaryops.v" % objfile
if path.exists("unaryops"): simulate_cmd = "vvp -m ../../../cosimulation/icarus/myhdl.vpi %s" % objfile
os.remove("unaryops") if path.exists(objfile):
os.remove(objfile)
os.system(analyze_cmd) os.system(analyze_cmd)
return Cosimulation(simulate_cmd, **locals()) return Cosimulation(simulate_cmd, **locals())
class TestUnaryOps(TestCase): class TestUnaryOps(TestCase):
@ -344,7 +349,7 @@ class TestUnaryOps(TestCase):
Not_v = Signal(bool(0)) Not_v = Signal(bool(0))
Invert = Signal(intbv(0)[m:]) Invert = Signal(intbv(0)[m:])
Invert_v = Signal(intbv(0)[m:]) Invert_v = Signal(intbv(0)[m:])
unaryops = toVerilog(unaryOps, unaryops = toVerilog(unaryOps,
Not, Not,
Invert, Invert,
@ -372,12 +377,12 @@ class TestUnaryOps(TestCase):
return unaryops, unaryops_v, stimulus(), check() return unaryops, unaryops_v, stimulus(), check()
def testUnaryOps(self): def testUnaryOps(self):
for m in (4, 7): for m in (4, 7):
sim = self.unaryBench(m) sim = self.unaryBench(m)
Simulation(sim).run() Simulation(sim).run()
if __name__ == '__main__': if __name__ == '__main__':
unittest.main() unittest.main()