FPGA/myhdl
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jand 2003-10-27 12:31:20 +00:00
parent 7a8176eed9
commit d7b3c0b892
2 changed files with 0 additions and 6 deletions
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5
myhdl/test/toVerilog/test_NotSupported.py
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@ -218,7 +218,6 @@ class TestNotSupported(unittest.TestCase):
z.next = 1
return
self.check(g, z, a)
def testTryExcept(self):
a = Signal(bool())
@ -264,10 +263,6 @@ class TestNotSupported(unittest.TestCase):
z.next = -a
return
self.check(g, z, a)
if __name__ == '__main__':

1
myhdl/test/toVerilog/test_ops.py
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@ -183,7 +183,6 @@ class TestBinaryOps(TestCase):
self.assertEqual(Bitxor, Bitxor_v)
self.assertEqual(FloorDiv, FloorDiv_v)
self.assertEqual(LeftShift, LeftShift_v)
print LeftShift
self.assertEqual(Mod, Mod_v)
self.assertEqual(Mul, Mul_v)
self.assertEqual(RightShift, RightShift_v)