test for ord support

myhdl/conversion/_analyze.py

@@ -507,7 +507,7 @@ class _AnalyzeVisitor(_ConversionMixin):
             node.obj = int(0) # XXX
         elif f is bool:
             node.obj = bool()
-        elif f is int:
+        elif f in (int, long, ord):
             node.obj = int(-1)
 ##         elif f in (posedge , negedge):
 ##             node.obj = _EdgeDetector()
@@ -768,7 +768,6 @@ class _AnalyzeVisitor(_ConversionMixin):
         
     def visitPrintnl(self, node, *args):
         self.ast.hasPrint = True
-        node.format = "%s"
         n = node.nodes[0]
         if isinstance(n, astNode.Mod) and \
            (isinstance(n.left, astNode.Const) and isinstance(n.left.value, str)):

myhdl/conversion/_toVHDL.py

@@ -1753,7 +1753,7 @@ class _AnnotateTypesVisitor(_ConversionMixin):
             node.vhd = vhd_unsigned(s)
         elif f is bool:
             node.vhd = vhd_boolean()
-        elif f is int:
+        elif f in (int, long, ord):
             node.vhd = vhd_int()
             node.args[0].vhd = vhd_int()
         elif f is intbv:

myhdl/test/conversion/general/test_print.py

@@ -43,11 +43,17 @@ def PrintBench():
         print b
         print "%% %s" % i1
         yield delay(10)
+        
 #        print state
 ##         print "the state is %s" % state
 ##         print "the state is %s" % (state,)
 ##         print "i1 is %s and the state is %s" % (i1, state)
 
+        yield delay(10)
+        # ord test
+        print ord('y')
+        print ord('2')
+
     return logic
 
 def testPrint():