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Release 0.11.42 (#400)

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Josy Boelen 2022-12-18 21:17:40 +01:00 committed by GitHub
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myhdl/__init__.py
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@ -49,7 +49,7 @@ traceSignals -- function that enables signal tracing in a VCD file
toVerilog -- function that converts a design to Verilog toVerilog -- function that converts a design to Verilog
""" """
__version__ = "0.11" __version__ = "0.11.42"
class StopSimulation(Exception): class StopSimulation(Exception):