Use module decorator in qualified way

cosimulation/test/bin2gray.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 def bin2gray(B, G, width):

cosimulation/test/dff.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 ACTIVE_LOW, INACTIVE_HIGH = 0, 1

cosimulation/test/dff_clkout.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 from dff import dff

cosimulation/test/inc.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 ACTIVE_LOW, INACTIVE_HIGH = 0, 1

example/arith_lib/Dec.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 from arith_utils import BEHAVIOR
 from PrefixAnd import PrefixAnd

example/arith_lib/LeadZeroDet.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 from arith_utils import BEHAVIOR
 from PrefixAnd import PrefixAnd

example/arith_lib/PrefixAnd.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 from arith_utils import log2ceil

example/arith_lib/test_Dec.py

@@ -1,6 +1,7 @@
 import unittest
 from unittest import TestCase
 
+import myhdl
 from myhdl import *
 
 from arith_utils import BEHAVIOR, STRUCTURE

example/arith_lib/test_LeadZeroDet.py

@@ -1,6 +1,7 @@
 import unittest
 from unittest import TestCase
 
+import myhdl
 from myhdl import *
 
 from arith_utils import BEHAVIOR, STRUCTURE

example/cookbook/bitonic/bitonic.py

@@ -1,11 +1,12 @@
 import subprocess
 
+import myhdl
 from myhdl import *
 from myhdl.conversion import analyze
 
 DESCENDING, ASCENDING = False, True
 
-@module
+@myhdl.module
 def comp(a1, a2, z1, z2, dir):
 
     @always_comb
@@ -19,7 +20,7 @@ def comp(a1, a2, z1, z2, dir):
     return logic
 
 
-@module
+@myhdl.module
 def feedthru(a, z):
 
     @always_comb
@@ -29,7 +30,7 @@ def feedthru(a, z):
     return logic
 
 
-@module
+@myhdl.module
 def bitonicMerge(a, z, dir):
 
     n = len(a)
@@ -48,7 +49,7 @@ def bitonicMerge(a, z, dir):
         return feedthru(a[0], z[0])
 
 
-@module
+@myhdl.module
 def bitonicSort(a, z, dir):
 
     n = len(a)
@@ -67,7 +68,7 @@ def bitonicSort(a, z, dir):
     else:
         return feedthru(a[0], z[0])
 
-@module
+@myhdl.module
 def Array8Sorter(a0, a1, a2, a3, a4, a5, a6, a7,
                  z0, z1, z2, z3, z4, z5, z6, z7):
 

example/cookbook/bitonic/test_bitonic.py

@@ -1,18 +1,19 @@
 from random import randrange
 
+import myhdl
 from myhdl import *
 
 from bitonic import Array8Sorter, Array8Sorter_v
 
 def bench():
-    
+
     n = 8
     w = 4
-    
+
     a0, a1, a2, a3, a4, a5, a6, a7 = inputs = [Signal(intbv(0)[w:]) for i in range(n)]
     z0, z1, z2, z3, z4, z5, z6, z7 = outputs = [Signal(intbv(0)[w:]) for i in range(n)]
 
-    
+
     inst = Array8Sorter_v(a0, a1, a2, a3, a4, a5, a6, a7,
                           z0, z1, z2, z3, z4, z5, z6, z7)
 
@@ -35,6 +36,3 @@ def test_bench():
 
 if __name__ == '__main__':
     test_bench()
-
-
-    

example/cookbook/dff/dff.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 from myhdl.conversion import analyze
 

example/cookbook/dffa/dffa.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 def dffa(q, d, clk, rst):

example/cookbook/johnson/jc2.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 ACTIVE = 0

example/cookbook/johnson/jc2_alt.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 ACTIVE = 0

example/cookbook/johnson/test_jc2.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 ACTIVE, INACTIVE = bool(0), bool(1)

example/cookbook/latch/latch.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 def latch(q, d, g):

example/cookbook/sinecomp/SineComputer.py

@@ -1,5 +1,6 @@
 from math import atan, sqrt, ceil, floor, pi
 
+import myhdl
 from myhdl import *
 
 t_State = enum("WAITING", "CALCULATING")

example/cookbook/sinecomp/test_SineComputer.py

@@ -1,6 +1,7 @@
 from math import pi, sin, cos, log
 import random
 
+import myhdl
 from myhdl import *
 
 from SineComputer import SineComputer, SineComputer_v

example/cookbook/stopwatch/StopWatch.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 from TimeCount import TimeCount

example/cookbook/stopwatch/TimeCount.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 def TimeCount(tens, ones, tenths, startstop, reset, clock):

example/cookbook/stopwatch/bcd2led.py

@@ -1,5 +1,6 @@
 import seven_segment
 
+import myhdl
 from myhdl import *
 
 code = [None] * 10

example/cookbook/stopwatch/test_TimeCount.py

@@ -1,5 +1,6 @@
 from random import randrange
 
+import myhdl
 from myhdl import *
 
 from TimeCount import TimeCount

example/cookbook/stopwatch/test_bcd2led.py

@@ -1,5 +1,6 @@
 from random import randrange
 import seven_segment
+import myhdl
 from myhdl import *
 from bcd2led import bcd2led
 

example/manual/GrayInc.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 from bin2gray2 import bin2gray

example/manual/bin2gray2.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 def bin2gray(B, G, width):

example/manual/custom.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 def inc_comb(nextCount, count, n):

example/manual/fifo.py

@@ -1,6 +1,7 @@
 import sys
 import traceback
 
+import myhdl
 from myhdl import *
 
 class Error(Exception):

example/manual/fsm.py

@@ -1,10 +1,11 @@
+import myhdl
 from myhdl import *
 
 ACTIVE_LOW = 0
 FRAME_SIZE = 8
 t_State = enum('SEARCH', 'CONFIRM', 'SYNC')
 
-@module
+@myhdl.module
 def FramerCtrl(SOF, state, syncFlag, clk, reset_n):
     
     """ Framing control FSM.
@@ -54,7 +55,7 @@ def FramerCtrl(SOF, state, syncFlag, clk, reset_n):
     return FSM
 
 
-@module
+@myhdl.module
 def testbench():
 
     SOF = Signal(bool(0))

example/manual/fsm2.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 # SEARCH, CONFIRM, SYNC = range(3)

example/manual/fsm3.py

@@ -1,6 +1,7 @@
 import os
 path = os.path
 
+import myhdl
 from myhdl import *
 
 # SEARCH, CONFIRM, SYNC = range(3)
@@ -9,7 +10,7 @@ ACTIVE_LOW = bool(0)
 FRAME_SIZE = 8
 t_State = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot")
 
-@module
+@myhdl.module
 def FramerCtrl(SOF, state, syncFlag, clk, reset_n):
     
     """ Framing control FSM.

example/manual/inc.py

@@ -1,4 +1,5 @@
 from random import randrange
+import myhdl
 from myhdl import *
 
 ACTIVE_LOW, INACTIVE_HIGH = 0, 1

example/manual/queue.py

@@ -1,5 +1,6 @@
 from __future__ import generators
 
+import myhdl
 from myhdl import *
 
 def trigger(event):

example/manual/ram.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 def ram(dout, din, addr, we, clk, depth=128):

example/manual/rom.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 CONTENT = (17, 134, 52, 9)

example/manual/shadow.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 from random import randrange

example/manual/sparseMemory.py

@@ -1,5 +1,6 @@
 import traceback
 
+import myhdl
 from myhdl import *
 
 

example/rs232/rs232_rx.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 from rs232_util import sec, parity, ParityError, StopBitError

example/rs232/rs232_tx.py

@@ -1,5 +1,6 @@
 import operator
 
+import myhdl
 from myhdl import *
 
 from rs232_util import reduceXor, sec, ODD, EVEN, MARK, SPACE

example/uart_tx/uart_tx.py

@@ -1,3 +1,4 @@
+import myhdl
 from myhdl import *
 
 def uart_tx(tx_bit, tx_valid, tx_byte, tx_clk, tx_rst):

myhdl/_module.py

@@ -17,7 +17,7 @@
 #  License along with this library; if not, write to the Free Software
 #  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 
-""" Module with the @module decorator function. """
+""" Module with the @myhdl.module decorator function. """
 from __future__ import absolute_import
 
 import inspect

myhdl/conversion/_analyze.py

@@ -31,6 +31,7 @@ import ast
 from itertools import chain
 from collections import defaultdict
 
+import myhdl
 import myhdl
 from myhdl import *
 from myhdl import ConversionError

myhdl/conversion/_misc.py

@@ -26,6 +26,7 @@ from __future__ import absolute_import
 import inspect
 import ast
 
+import myhdl
 import myhdl
 from myhdl import *
 from myhdl import ConversionError

myhdl/conversion/_toVHDL.py

@@ -38,6 +38,7 @@ import warnings
 from copy import copy
 import string
 
+import myhdl
 import myhdl
 from myhdl import *
 from myhdl import ToVHDLError, ToVHDLWarning

myhdl/conversion/_toVerilog.py

@@ -37,6 +37,7 @@ from types import GeneratorType
 from myhdl._compat import StringIO
 import warnings
 
+import myhdl
 import myhdl
 from myhdl import *
 from myhdl._compat import integer_types, class_types, PY2

myhdl/test/bugs/test_bug_1740778.py

@@ -6,6 +6,7 @@ import random
 from random import randrange
 random.seed(2)
 
+import myhdl
 from myhdl import *
 from myhdl.conversion import verify
 

myhdl/test/bugs/test_bug_1835792.py

@@ -6,6 +6,7 @@ import random
 from random import randrange
 random.seed(2)
 
+import myhdl
 from myhdl import *
 from myhdl.conversion import verify
 

myhdl/test/bugs/test_bug_1835797.py

@@ -6,6 +6,7 @@ import random
 from random import randrange
 random.seed(2)
 
+import myhdl
 from myhdl import *
 from myhdl.conversion import verify
 

myhdl/test/bugs/test_bug_1837003.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 from myhdl import ConversionError
 from myhdl.conversion._misc import _error

myhdl/test/bugs/test_bug_28.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 
 def bug_28(dout, channel):

myhdl/test/bugs/test_bug_3529686.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 
 def bug_3529686(clr, clk, run, ack, serialout):

myhdl/test/bugs/test_bug_3577799.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 from myhdl.conversion import analyze
 

myhdl/test/bugs/test_bug_39.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 from myhdl.conversion import verify
 

myhdl/test/bugs/test_bug_42.py

@@ -1,6 +1,7 @@
 from __future__ import absolute_import
 #! /usr/bin/env python
 
+import myhdl
 from myhdl import *
 
 def module(sigin, sigout):

myhdl/test/bugs/test_bug_42_2.py

@@ -1,6 +1,7 @@
 from __future__ import absolute_import
 #! /usr/bin/env python
 
+import myhdl
 from myhdl import *
 
 def module(sigin, sigout):

myhdl/test/bugs/test_bug_43.py

@@ -1,6 +1,7 @@
 from __future__ import absolute_import
 #! /usr/bin/env python
 
+import myhdl
 from myhdl import *
 
 def bug_43(sigin, sigout):

myhdl/test/bugs/test_bug_44.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 
 WIDTH=4

myhdl/test/bugs/test_bug_aj1s.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 from myhdl.conversion import verify
 

myhdl/test/bugs/test_bug_boolconst.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 
 INT_CONDITION_0 = 0 

myhdl/test/bugs/test_bug_boolop.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 
 def gray_counter (clk, reset, enable, gray_count):

myhdl/test/bugs/test_bug_enum_toVHDL.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 
 #t_state = enum('WAIT_POSEDGE', 'WAIT_NEGEDGE', encoding='one_hot')

myhdl/test/bugs/test_bug_enum_toVHDL_2.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 
 t_state = enum('WAIT_POSEDGE', 'WAIT_NEGEDGE', encoding='one_hot')

myhdl/test/bugs/test_issue_10_2.py

@@ -4,6 +4,7 @@
 """
 from __future__ import absolute_import
 
+import myhdl
 from myhdl import *
 from myhdl.conversion import verify
 

myhdl/test/bugs/test_issue_117.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 from myhdl.conversion import analyze
 

myhdl/test/bugs/test_issue_122.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 from myhdl.conversion import verify 
 

myhdl/test/bugs/test_issue_13.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 from myhdl.conversion import analyze
 

myhdl/test/bugs/test_issue_133.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 from myhdl.conversion import verify 
 

myhdl/test/bugs/test_issue_134.py

@@ -5,6 +5,7 @@ function is called multiple times, this causes name collisions """
 
 from __future__ import absolute_import
 import pytest
+import myhdl
 from myhdl import *
 from myhdl.conversion import analyze
 

myhdl/test/bugs/test_issue_18.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 from myhdl.conversion import analyze
 

myhdl/test/bugs/test_issue_40.py

@@ -1,6 +1,7 @@
 from __future__ import absolute_import
 #! /usr/bin/env python
 
+import myhdl
 from myhdl import *
 
 def mpegChannel(clk, rst):

myhdl/test/bugs/test_issue_9.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 
 def issue_9():

myhdl/test/bugs/test_issue_98.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 from myhdl.conversion import analyze
 

myhdl/test/conversion/general/test_ShadowSignal.py

@@ -1,7 +1,8 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 
-@module
+@myhdl.module
 def bench_SliceSignal():
 
     s = Signal(intbv(0)[8:])
@@ -29,7 +30,7 @@ def test_SliceSignal():
     assert conversion.verify(bench_SliceSignal()) == 0
 
 
-@module
+@myhdl.module
 def bench_ConcatSignal():
 
     a = Signal(intbv(0)[5:])
@@ -61,7 +62,7 @@ def bench_ConcatSignal():
 def test_ConcatSignal():
     assert conversion.verify(bench_ConcatSignal()) == 0
 
-@module
+@myhdl.module
 def bench_ConcatSignalWithConsts():
 
     a = Signal(intbv(0)[5:])
@@ -104,7 +105,7 @@ def test_ConcatSignalWithConsts():
     assert conversion.verify(bench_ConcatSignalWithConsts()) == 0
 
 
-@module
+@myhdl.module
 def bench_TristateSignal():
     s = TristateSignal(intbv(0)[8:])
     a = s.driver()
@@ -140,7 +141,7 @@ def test_TristateSignal():
     assert conversion.verify(bench_TristateSignal()) == 0
 
 
-@module
+@myhdl.module
 def permute(x, a, mapping):
 
     p = [a(m) for m in mapping]
@@ -154,7 +155,7 @@ def permute(x, a, mapping):
     return assign
 
 
-@module
+@myhdl.module
 def bench_permute(conv=False):
 
     x = Signal(intbv(0)[3:])

myhdl/test/conversion/general/test_adapter.py

@@ -1,7 +1,8 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 
-@module
+@myhdl.module
 def adapter(o_err, i_err, o_spec, i_spec):
 
     nomatch = Signal(bool(0))
@@ -35,14 +36,14 @@ def adapter(o_err, i_err, o_spec, i_spec):
     return assign
 
 
-@module
+@myhdl.module
 def bench_adapter(conv=False):
     o_spec = ('c', 'a', 'other', 'nomatch')
     i_spec = { 'a' : 1, 'b' : 2, 'c' : 0, 'd' : 3, 'e' : 4, 'f' : 5, }
 
     o_err = Signal(intbv(0)[4:])
     i_err = Signal(intbv(0)[6:])
-    
+
     if conv:
         dut = conv(adapter(o_err, i_err, o_spec, i_spec))
     else:

myhdl/test/conversion/general/test_bin2gray.py

@@ -2,10 +2,11 @@ from __future__ import absolute_import
 import os
 path = os.path
 
+import myhdl
 from myhdl import *
 from myhdl.conversion import verify
 
-@module
+@myhdl.module
 def bin2gray2(B, G, width):
     """ Gray encoder.
 
@@ -23,7 +24,7 @@ def bin2gray2(B, G, width):
                 G.next[i] = Bext[i+1] ^ Bext[i]
     return logic
 
-@module
+@myhdl.module
 def bin2gray(B, G, width):
 
     """ Gray encoder.
@@ -44,7 +45,7 @@ def bin2gray(B, G, width):
     return logic
 
 
-@module
+@myhdl.module
 def bin2grayBench(width, bin2gray):
 
     B = Signal(intbv(0)[width:])

myhdl/test/conversion/general/test_case.py

@@ -1,7 +1,8 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 
-@module
+@myhdl.module
 def map_case4(z, a):
 
     @always_comb
@@ -17,7 +18,7 @@ def map_case4(z, a):
 
     return logic
 
-@module
+@myhdl.module
 def map_case2(z, a):
 
     @always_comb
@@ -30,7 +31,7 @@ def map_case2(z, a):
 
     return logic
 
-@module
+@myhdl.module
 def map_case3(z, a):
 
     @always_comb
@@ -44,7 +45,7 @@ def map_case3(z, a):
 
     return logic
 
-@module
+@myhdl.module
 def map_case4_full(z, a):
 
     @always_comb
@@ -61,7 +62,7 @@ def map_case4_full(z, a):
     return logic
 
 
-@module
+@myhdl.module
 def bench_case(map_case, N):
 
     a = Signal(intbv(0)[2:])

myhdl/test/conversion/general/test_constants.py

@@ -1,7 +1,8 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 
-@module
+@myhdl.module
 def constants(v, u, x, y, z, a):
 
     b = Signal(bool(0))

myhdl/test/conversion/general/test_dec.py

@@ -5,13 +5,14 @@ import random
 from random import randrange
 random.seed(2)
 
+import myhdl
 from myhdl import *
 from myhdl.conversion import verify
 
 ACTIVE_LOW, INACTIVE_HIGH = 0, 1
 
 
-@module
+@myhdl.module
 def decRef(count, enable, clock, reset, n):
     """ Decrementer with enable.
     
@@ -36,7 +37,7 @@ def decRef(count, enable, clock, reset, n):
     return logic
                     
                 
-@module
+@myhdl.module
 def dec(count, enable, clock, reset, n):
     """ Decrementer with enable.
     
@@ -61,7 +62,7 @@ def dec(count, enable, clock, reset, n):
     return decProcess
 
 
-@module
+@myhdl.module
 def decFunc(count, enable, clock, reset, n):
 
     def decFuncFunc(cnt):
@@ -83,7 +84,7 @@ def decFunc(count, enable, clock, reset, n):
     return decFuncGen
 
 
-@module
+@myhdl.module
 def decTask(count, enable, clock, reset, n):
     
     def decTaskFunc(cnt, enable, reset, n):
@@ -109,7 +110,7 @@ def decTask(count, enable, clock, reset, n):
     return decTaskGen
 
 
-@module
+@myhdl.module
 def decTaskFreeVar(count, enable, clock, reset, n):
     
     def decTaskFunc():
@@ -132,7 +133,7 @@ def decTaskFreeVar(count, enable, clock, reset, n):
     return decTaskGen
 
 
-@module
+@myhdl.module
 def DecBench(dec):
     
     m = 8

myhdl/test/conversion/general/test_errors.py

@@ -1,11 +1,12 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 from myhdl import ConversionError
 from myhdl.conversion._misc import _error
 from myhdl.conversion import verify
 
 
-@module
+@myhdl.module
 def sigAugmAssignUnsupported(z, a):
     @always(a)
     def logic():
@@ -22,7 +23,7 @@ def test_SigAugmAssignUnsupported():
     else:
         assert False
         
-@module
+@myhdl.module
 def modbvRange(z, a, b):
     @always(a, b)
     def logic():
@@ -42,7 +43,7 @@ def test_modbvRange():
     else:
         assert False
         
-@module
+@myhdl.module
 def modbvSigRange(z, a, b):
     @always(a, b)
     def logic():

myhdl/test/conversion/general/test_fsm.py

@@ -2,6 +2,7 @@ from __future__ import absolute_import
 import os
 path = os.path
 
+import myhdl
 from myhdl import *
 from myhdl.conversion import verify
 
@@ -12,7 +13,7 @@ t_State_b = enum('SEARCH', 'CONFIRM', 'SYNC')
 t_State_oh = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_hot")
 t_State_oc = enum('SEARCH', 'CONFIRM', 'SYNC', encoding="one_cold")
 
-@module
+@myhdl.module
 def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State):
     
     """ Framing control FSM.
@@ -56,7 +57,7 @@ def FramerCtrl(SOF, state, syncFlag, clk, reset_n, t_State):
             
     return FSM
 
-@module
+@myhdl.module
 def FSMBench(FramerCtrl, t_State):
 
     SOF = Signal(bool(0))

myhdl/test/conversion/general/test_hec.py

@@ -3,6 +3,7 @@ import os
 path = os.path
 from random import randrange
 
+import myhdl
 from myhdl import *
 from myhdl.conversion import verify
 
@@ -57,7 +58,7 @@ def calculateHecTask(hec, header):
     h ^= COSET
     hec[:] = h
 
-@module
+@myhdl.module
 def HecCalculatorPlain(hec, header):
     """ Hec calculation module.
 
@@ -125,7 +126,7 @@ headers = [ 0x00000000,
 headers.extend([randrange(2**32-1) for i in range(10)])
 headers = tuple(headers)
 
-@module
+@myhdl.module
 def HecBench(HecCalculator):
 
     hec = Signal(intbv(0)[8:])

myhdl/test/conversion/general/test_inc.py

@@ -6,13 +6,14 @@ import random
 from random import randrange
 random.seed(2)
 
+import myhdl
 from myhdl import *
 from myhdl.conversion import verify
 
 
 ACTIVE_LOW, INACTIVE_HIGH = bool(0), bool(1)
 
-@module
+@myhdl.module
 def incRef(count, enable, clock, reset, n):
     """ Incrementer with enable.
     
@@ -33,7 +34,7 @@ def incRef(count, enable, clock, reset, n):
                     count.next = (count + 1) % n
     return logic
                 
-@module
+@myhdl.module
 def inc(count, enable, clock, reset, n):
     
     """ Incrementer with enable.
@@ -56,7 +57,7 @@ def inc(count, enable, clock, reset, n):
                 
     return incProcess
 
-@module
+@myhdl.module
 def inc2(count, enable, clock, reset, n):
     
     @always(clock.posedge, reset.negedge)
@@ -72,7 +73,7 @@ def inc2(count, enable, clock, reset, n):
     return incProcess
 
 
-@module
+@myhdl.module
 def incFunc(count, enable, clock, reset, n):
     def incFuncFunc(cnt, enable):
         count_next = intbv(0, min=0, max=n)
@@ -91,7 +92,7 @@ def incFunc(count, enable, clock, reset, n):
     return incFuncGen
     
 
-@module
+@myhdl.module
 def incTask(count, enable, clock, reset, n):
     
     def incTaskFunc(cnt, enable, reset, n):
@@ -114,7 +115,7 @@ def incTask(count, enable, clock, reset, n):
     return incTaskGen
 
 
-@module
+@myhdl.module
 def incTaskFreeVar(count, enable, clock, reset, n):
     
     def incTaskFunc():
@@ -132,7 +133,7 @@ def incTaskFreeVar(count, enable, clock, reset, n):
     return incTaskGen
 
 
-@module
+@myhdl.module
 def IncBench(inc):
 
     NR_CYCLES = 201

myhdl/test/conversion/general/test_intbv_signed.py

@@ -21,9 +21,10 @@
 """ Run the intbv.signed() unit tests. """
 from __future__ import absolute_import
 
+import myhdl
 from myhdl import *
 
-@module
+@myhdl.module
 def PlainIntbv():
     '''Test a plain intbv instance with .signed() 
 
@@ -197,7 +198,7 @@ def PlainIntbv():
 
 
 
-@module
+@myhdl.module
 def SlicedSigned():
     '''Test a slice with .signed()
 
@@ -224,7 +225,7 @@ def SlicedSigned():
     return logic
 
 
-@module
+@myhdl.module
 def SignedConcat():
     '''Test the .signed() function with the concatenate function'''
 

myhdl/test/conversion/general/test_interfaces1.py

@@ -2,6 +2,7 @@ from __future__ import absolute_import
 
 import sys
 
+import myhdl
 from myhdl import *
 from myhdl import ConversionError
 from myhdl.conversion._misc import _error
@@ -12,7 +13,7 @@ class MyIntf(object):
         self.x = Signal(intbv(2,min=0,max=16))
         self.y = Signal(intbv(3,min=0,max=18))
 
-@module
+@myhdl.module
 def m_one_level(clock,reset,ia,ib):
 
     @always_seq(clock.posedge,reset=reset)
@@ -22,7 +23,7 @@ def m_one_level(clock,reset,ia,ib):
 
     return rtl
 
-@module
+@myhdl.module
 def m_two_level(clock,reset,ia,ib):
 
     ic,ie = (MyIntf(),MyIntf(),)
@@ -34,7 +35,7 @@ def m_two_level(clock,reset,ia,ib):
 
     return g_one, rtl
 
-@module
+@myhdl.module
 def c_testbench_one():
     clock = Signal(bool(0))
     reset = ResetSignal(0,active=0,async=True)
@@ -66,7 +67,7 @@ def c_testbench_one():
 
     return tb_dut, tb_clk, tb_stim
 
-@module
+@myhdl.module
 def c_testbench_two():
     clock = Signal(bool(0))
     reset = ResetSignal(0,active=0,async=True)

myhdl/test/conversion/general/test_interfaces2.py

@@ -2,6 +2,7 @@ from __future__ import absolute_import
 
 import sys
 
+import myhdl
 from myhdl import *
 from myhdl.conversion import analyze,verify
 
@@ -11,7 +12,7 @@ class Intf(object):
         self.y = Signal(intbv(2,min=-2211,max=2211))
         self.z = Signal(intbv(3,min=-3311,max=3311))
 
-@module
+@myhdl.module
 def m_modify(clock,reset,a):
 
     intfa = Intf()
@@ -30,7 +31,7 @@ def m_modify(clock,reset,a):
 
     return rtl_inc,rtl_add
 
-@module
+@myhdl.module
 def m_test_intf(clock,reset,a,b,c):
 
     intfa = Intf()
@@ -61,7 +62,7 @@ def m_test_intf(clock,reset,a,b,c):
     return gen_mod,rtl_inc,rtl_combine
 
 
-@module
+@myhdl.module
 def name_conflict_after_replace(clock, reset, a, a_x):
     a_x_0 = [Signal(intbv(0)[len(a_x):]) for i in range(8)]
 
@@ -80,7 +81,7 @@ def test_name_conflict_after_replace():
     a_x = Signal(intbv(0)[len(a.x):])
     assert conversion.analyze(name_conflict_after_replace(clock, reset, a, a_x)) == 0
 
-@module
+@myhdl.module
 def c_testbench():
     clock = Signal(bool(0))
     reset = ResetSignal(0, active=0, async=False)

myhdl/test/conversion/general/test_interfaces3.py

@@ -4,11 +4,13 @@ import sys
 
 import pytest
 
+import myhdl
 from myhdl import *
 from myhdl import ConversionError
 from myhdl.conversion._misc import _error
 from myhdl.conversion import analyze, verify
 
+import myhdl
 from myhdl import *
 
 
@@ -42,14 +44,14 @@ class IntfWithConstant2:
         self.more_constants = IntfWithConstant1()
 
 
-@module
+@myhdl.module
 def m_assign(y, x):
     @always_comb
     def assign():
         y.next = x
     return assign
 
-@module
+@myhdl.module
 def m_top_assign(x,y,z):
     """
     This module does not test top-level interfaces,
@@ -63,14 +65,14 @@ def m_top_assign(x,y,z):
 
     return ga1, ga2, gm1
 
-@module
+@myhdl.module
 def m_assign_intf(x, y):
     @always_comb
     def rtl():
         x.x.next = y.y
     return rtl
 
-@module
+@myhdl.module
 def c_testbench_one():
     x,y,z = [Signal(intbv(0, min=-8, max=8))
              for _ in range(3)]
@@ -85,7 +87,7 @@ def c_testbench_one():
         
     return tb_dut, tb_stim
         
-@module
+@myhdl.module
 def m_top_multi_comb(x,y,z):
     """
     This module does not test top-level interfaces,
@@ -98,14 +100,14 @@ def m_top_multi_comb(x,y,z):
     gm = m_multi_comb(*intf)
     return gm
 
-@module
+@myhdl.module
 def m_multi_comb(x, y, z):
     @always_comb
     def rtl():
         x.x.next = y.y + z.z.z
     return rtl
 
-@module
+@myhdl.module
 def c_testbench_two():
     x,y,z = [Signal(intbv(0, min=-8, max=8))
              for _ in range(3)]
@@ -121,7 +123,7 @@ def c_testbench_two():
     return tb_dut, tb_stim
     
 
-@module
+@myhdl.module
 def m_top_const(clock, reset, x, y, intf):
 
     @always_seq(clock.posedge, reset=reset)
@@ -136,7 +138,7 @@ def m_top_const(clock, reset, x, y, intf):
 
     return rtl1, rtl2
 
-@module
+@myhdl.module
 def c_testbench_three():
     """
     this will test the use of constants in an inteface

myhdl/test/conversion/general/test_interfaces4.py

@@ -2,11 +2,13 @@ from __future__ import absolute_import
 
 import sys
 
+import myhdl
 from myhdl import *
 from myhdl import ConversionError
 from myhdl.conversion._misc import _error
 from myhdl.conversion import analyze, verify
 
+import myhdl
 from myhdl import *
 
 """
@@ -30,7 +32,7 @@ class Intf2(object):
         self.sig3 = Signal(modbv(0)[8:])
         self.intf = Intf1()
 
-@module
+@myhdl.module
 def mod1(clock, reset, intf1, intf2):
     
     sig1 = Signal(bool(0))
@@ -51,7 +53,7 @@ def mod1(clock, reset, intf1, intf2):
     return proc
 
 
-@module
+@myhdl.module
 def mod2(clock, reset, intf1, intf2):
     @always_seq(clock.posedge, reset)
     def proc():
@@ -68,7 +70,7 @@ def mod2(clock, reset, intf1, intf2):
     return proc
 
 
-@module
+@myhdl.module
 def m_top(clock, reset, sdi, sdo):
     
     intf1 = Intf1()
@@ -88,7 +90,7 @@ def m_top(clock, reset, sdi, sdo):
     return g1, g2, assigns
 
 
-@module
+@myhdl.module
 def c_testbench_one():
     """ yet another interface test.
     This test is used to expose a particular bug that was discovered

myhdl/test/conversion/general/test_listofsigs.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 from myhdl import ConversionError
 from myhdl.conversion._misc import _error
@@ -9,7 +10,7 @@ M= 2**N
 
 ### A first case that already worked with 5.0 list of signal constraints ###
 
-@module
+@myhdl.module
 def intbv2list():
     """Conversion between intbv and list of boolean signals."""
     
@@ -46,7 +47,7 @@ def test_intbv2list():
     
 ### A number of cases with relaxed constraints, for various decorator types ###
 
-@module
+@myhdl.module
 def inv1(z, a):
     @always(a)
     def logic():
@@ -54,7 +55,7 @@ def inv1(z, a):
     return logic
 
 
-@module
+@myhdl.module
 def inv2(z, a):
     @always_comb
     def logic():
@@ -62,7 +63,7 @@ def inv2(z, a):
     return logic
 
 
-@module
+@myhdl.module
 def inv3(z, a):
     @instance
     def logic():
@@ -71,7 +72,7 @@ def inv3(z, a):
             z.next = not a
     return logic
 
-@module
+@myhdl.module
 def inv4(z, a):
     @instance
     def logic():
@@ -82,7 +83,7 @@ def inv4(z, a):
     return logic
 
 
-@module
+@myhdl.module
 def case1(z, a, inv):
     b = [Signal(bool(1)) for i in range(len(a))]
     c = [Signal(bool(0)) for i in range(len(a))]
@@ -103,7 +104,7 @@ def case1(z, a, inv):
     return extract, inst, assemble
 
 
-@module
+@myhdl.module
 def case2(z, a, inv):
     b = [Signal(bool(1)) for i in range(len(a))]
     c = [Signal(bool(0)) for i in range(len(a))]
@@ -124,7 +125,7 @@ def case2(z, a, inv):
     return extract, inst, assemble
 
 
-@module
+@myhdl.module
 def case3(z, a, inv):
     b = [Signal(bool(1)) for i in range(len(a))]
     c = [Signal(bool(0)) for i in range(len(a))]
@@ -149,7 +150,7 @@ def case3(z, a, inv):
     return extract, inst, assemble
 
 
-@module
+@myhdl.module
 def case4(z, a, inv):
     b = [Signal(bool(1)) for i in range(len(a))]
     c = [Signal(bool(0)) for i in range(len(a))]
@@ -180,7 +181,7 @@ def case4(z, a, inv):
 
 
 
-@module
+@myhdl.module
 def processlist(case, inv):
     """Extract list from intbv, do some processing, reassemble."""
     
@@ -222,7 +223,7 @@ def test_processlist44():
 
 
 # signed and unsigned
-@module
+@myhdl.module
 def unsigned():
     z = Signal(intbv(0)[8:])
     a = [Signal(intbv(0)[8:]) for i in range(3)]
@@ -245,7 +246,7 @@ def test_unsigned():
     conversion.verify(unsigned())
         
 
-@module
+@myhdl.module
 def signed():
     z = Signal(intbv(0, min=-10, max=34))
     a = [Signal(intbv(0, min=-5, max=17)) for i in range(3)]
@@ -268,7 +269,7 @@ def test_signed():
     conversion.verify(signed())
         
 
-@module
+@myhdl.module
 def mixed():
     z = Signal(intbv(0, min=0, max=34))
     a = [Signal(intbv(0, min=-11, max=17)) for i in range(3)]
@@ -296,7 +297,7 @@ def test_mixed():
 
 # port in list
 
-@module
+@myhdl.module
 def portInList(z, a, b):
 
     m = [a, b]
@@ -321,7 +322,7 @@ def test_portInList():
     
 # signal in multiple lists
 
-@module
+@myhdl.module
 def sigInMultipleLists():
 
     z, a, b = [Signal(intbv(0)[8:]) for i in range(3)]
@@ -346,7 +347,7 @@ def test_sigInMultipleLists():
 
 # list of signals as port
        
-@module
+@myhdl.module
 def my_register(clk, inp, outp):
     @always(clk.posedge)
     def my_register_impl():

myhdl/test/conversion/general/test_loops.py

@@ -4,12 +4,13 @@ path = os.path
 from random import randrange
 
 
+import myhdl
 from myhdl import *
 from myhdl.conversion import verify, analyze
 from myhdl import ConversionError
 from myhdl.conversion._misc import _error
 
-@module
+@myhdl.module
 def ForLoopError1(a, out):
     @instance
     def logic():
@@ -22,7 +23,7 @@ def ForLoopError1(a, out):
             out.next = var
     return logic
         
-@module
+@myhdl.module
 def ForLoopError2(a, out):
     @instance
     def logic():
@@ -35,7 +36,7 @@ def ForLoopError2(a, out):
             out.next = var
     return logic
 
-@module
+@myhdl.module
 def ForLoop1(a, out):
     @instance
     def logic():
@@ -48,7 +49,7 @@ def ForLoop1(a, out):
             out.next = var
     return logic
 
-@module
+@myhdl.module
 def ForLoop2(a, out):
     @instance
     def logic():
@@ -61,7 +62,7 @@ def ForLoop2(a, out):
             out.next = var
     return logic
 
-@module
+@myhdl.module
 def ForLoop3(a, out):
     @instance
     def logic():
@@ -74,7 +75,7 @@ def ForLoop3(a, out):
             out.next = var
     return logic
         
-@module
+@myhdl.module
 def ForLoop4(a, out):
     @instance
     def logic():
@@ -87,7 +88,7 @@ def ForLoop4(a, out):
             out.next = var
     return logic
 
-@module
+@myhdl.module
 def ForLoop5(a, out):
     @instance
     def logic():
@@ -100,7 +101,7 @@ def ForLoop5(a, out):
             out.next = var
     return logic
 
-@module
+@myhdl.module
 def ForLoop6(a, out):
     @instance
     def logic():
@@ -113,7 +114,7 @@ def ForLoop6(a, out):
             out.next = var
     return logic
 
-@module
+@myhdl.module
 def ForContinueLoop(a, out):
     @instance
     def logic():
@@ -127,7 +128,7 @@ def ForContinueLoop(a, out):
             out.next = var
     return logic
 
-@module
+@myhdl.module
 def ForBreakLoop(a, out):
     @instance
     def logic():
@@ -140,7 +141,7 @@ def ForBreakLoop(a, out):
                     break
     return logic
 
-@module
+@myhdl.module
 def ForBreakContinueLoop(a, out):
     @instance
     def logic():
@@ -154,7 +155,7 @@ def ForBreakContinueLoop(a, out):
                 break
     return logic
 
-@module
+@myhdl.module
 def NestedForLoop1(a, out):
     @instance
     def logic():
@@ -172,7 +173,7 @@ def NestedForLoop1(a, out):
             out.next = var
     return logic
 
-@module
+@myhdl.module
 def NestedForLoop2(a, out):
     @instance
     def logic():
@@ -199,7 +200,7 @@ def ReturnFromFunction(a):
             return i
     return 0
 
-@module
+@myhdl.module
 def FunctionCall(a, out):
     @instance
     def logic():
@@ -218,7 +219,7 @@ def ReturnFromTask(a, out):
             return
     out[:] = 23 # to notice it
 
-@module
+@myhdl.module
 def TaskCall(a, out):
     @instance
     def logic():
@@ -229,7 +230,7 @@ def TaskCall(a, out):
             out.next = var
     return logic
 
-@module
+@myhdl.module
 def WhileLoop(a, out):
     @instance
     def logic():
@@ -244,7 +245,7 @@ def WhileLoop(a, out):
             out.next = var
     return logic
 
-@module
+@myhdl.module
 def WhileContinueLoop(a, out):
     @instance
     def logic():
@@ -261,7 +262,7 @@ def WhileContinueLoop(a, out):
             out.next = var
     return logic
         
-@module
+@myhdl.module
 def WhileBreakLoop(a, out):
     @instance
     def logic():
@@ -277,7 +278,7 @@ def WhileBreakLoop(a, out):
                 i -= 1
     return logic
     
-@module
+@myhdl.module
 def WhileBreakContinueLoop(a, out):
     @instance
     def logic():
@@ -294,7 +295,7 @@ def WhileBreakContinueLoop(a, out):
                 break
     return logic
     
-@module
+@myhdl.module
 def LoopBench(LoopTest):
 
     a = Signal(intbv(-1)[16:])

myhdl/test/conversion/general/test_method.py

@@ -1,5 +1,6 @@
 from __future__ import absolute_import
 import sys
+import myhdl
 from myhdl import *
 from myhdl.conversion import verify
 
@@ -7,7 +8,7 @@ class HdlObj(object):
     def __init__(self):
         pass
 
-    @module
+    @myhdl.module
     def method_func(self, clk, srst, x, y):
         z = Signal(intbv(0, min=y.min, max=y.max))
         ifx = self._mfunc(x, z)
@@ -20,14 +21,14 @@ class HdlObj(object):
 
         return hdl, ifx
 
-    @module
+    @myhdl.module
     def _mfunc(self, x, y):
         @always_comb
         def _hdl():
             y.next = x + 1
         return _hdl
 
-@module
+@myhdl.module
 def _func(x,y):
     @always_comb
     def _hdl():
@@ -38,7 +39,7 @@ class HdlObjObj(object):
     def __init__(self):
         pass
     
-    @module
+    @myhdl.module
     def method_func(self, clk, srst, x, y):
         z1 = Signal(intbv(0, min=y.min, max=y.max))
         z2 = Signal(intbv(0, min=y.min, max=y.max))
@@ -59,7 +60,7 @@ class HdlObjAttrSimple(object):
     def __init__(self):
         self.AConstant = 3
 
-    @module
+    @myhdl.module
     def method_func(self, clk, srst, x, y):
         
         # limitation for class method conversion, the object attributes
@@ -83,7 +84,7 @@ class HdlObjAttr(object):
         self.z = Signal(intbv(0, min=y.min, max=y.max))
         self.hobj = HdlObj()
         
-    @module
+    @myhdl.module
     def method_func(self):
         ifx = self.hobj._mfunc(self.x, self.z)
         @always(self.clk.posedge)
@@ -95,7 +96,7 @@ class HdlObjAttr(object):
 
         return hdl, ifx
 
-@module
+@myhdl.module
 def ObjBench(hObj):
 
     clk = Signal(False)

myhdl/test/conversion/general/test_nonlocal.py

@@ -2,6 +2,7 @@ from __future__ import absolute_import
 import os
 path = os.path
 
+import myhdl
 from myhdl import *
 
 

myhdl/test/conversion/general/test_numass.py

@@ -1,10 +1,11 @@
 from __future__ import absolute_import
 from random import randrange
 
+import myhdl
 from myhdl import *
 
 
-@module
+@myhdl.module
 def NumassBench():
 
     p = Signal(intbv(1)[8:])

myhdl/test/conversion/general/test_print.py

@@ -1,4 +1,5 @@
 from __future__ import absolute_import
+import myhdl
 from myhdl import *
 from myhdl import ConversionError
 from myhdl.conversion._misc import _error

myhdl/test/conversion/general/test_ram.py

@@ -3,9 +3,10 @@ import os
 path = os.path
 import unittest
 
+import myhdl
 from myhdl import *
 
-@module
+@myhdl.module
 def ram1(dout, din, addr, we, clk, depth=128):
     """ Simple ram model """
 
@@ -21,7 +22,7 @@ def ram1(dout, din, addr, we, clk, depth=128):
             dout.next = mem[int(addr)]
     return logic
 
-@module
+@myhdl.module
 def ram_clocked(dout, din, addr, we, clk, depth=128):
     """ Ram model """
     
@@ -37,7 +38,7 @@ def ram_clocked(dout, din, addr, we, clk, depth=128):
             
     return access
 
-@module
+@myhdl.module
 def ram_deco1(dout, din, addr, we, clk, depth=128):
     """  Ram model """
     
@@ -57,7 +58,7 @@ def ram_deco1(dout, din, addr, we, clk, depth=128):
     return write, read
 
 
-@module
+@myhdl.module
 def ram_deco2(dout, din, addr, we, clk, depth=128):
     """  Ram model """
     
@@ -75,7 +76,7 @@ def ram_deco2(dout, din, addr, we, clk, depth=128):
     return write, read
 
 
-@module
+@myhdl.module
 def ram2(dout, din, addr, we, clk, depth=128):
         
     memL = [Signal(intbv()[len(dout):]) for i in range(depth)]
@@ -96,7 +97,7 @@ def ram2(dout, din, addr, we, clk, depth=128):
     return wrLogic, rdLogic
 
 
-@module
+@myhdl.module
 def RamBench(ram, depth=128):
 
     dout = Signal(intbv(0)[8:])

myhdl/test/conversion/general/test_randscrambler.py

@@ -9,6 +9,7 @@ from random import randrange
 random.seed(2)
 import time
 
+import myhdl
 from myhdl import *
 from myhdl.conversion import verify
 
@@ -16,7 +17,7 @@ N = 8
 M = 2 ** N
 DEPTH = 5
 
-@module
+@myhdl.module
 def xor(z, a, b, c):
     @instance
     def logic():
@@ -31,7 +32,7 @@ def randOthers(i, n):
     random.shuffle(l)
     return l[0], l[1]
 
-@module
+@myhdl.module
 def randscrambler(ol, il, stage=0):
     """ Recursive hierarchy of random xor gates.
 
@@ -59,7 +60,7 @@ def randscrambler(ol, il, stage=0):
             i1[i] = xor(ol[i], il[i], il[j], il[k])
         return i1
 
-@module
+@myhdl.module
 def randscrambler_top(o7, o6, o5, o4, o3, o2, o1, o0,
                     i7, i6, i5, i4, i3, i2, i1, i0):
     sl1 = [i7, i6, i5, i4, i3, i2, i1, i0]
@@ -71,7 +72,7 @@ o7, o6, o5, o4, o3, o2, o1, o0 = [Signal(bool()) for i in range(N)]
 i7, i6, i5, i4, i3, i2, i1, i0 = [Signal(bool()) for i in range(N)]
 v7, v6, v5, v4, v3, v2, v1, v0 = [Signal(bool()) for i in range(N)]
 
-@module
+@myhdl.module
 def randscramblerBench():
 
     @instance

myhdl/test/conversion/general/test_rom.py

@@ -3,13 +3,14 @@ import os
 path = os.path
 from random import randrange
 
+import myhdl
 from myhdl import *
 
 D = 256
 
 ROM = tuple([randrange(D) for i in range(D)])
 
-@module
+@myhdl.module
 def rom1(dout, addr, clk):
 
     @instance
@@ -20,7 +21,7 @@ def rom1(dout, addr, clk):
 
     return rdLogic
 
-@module
+@myhdl.module
 def rom2(dout, addr, clk):
     
     theROM = ROM
@@ -33,7 +34,7 @@ def rom2(dout, addr, clk):
 
     return rdLogic
 
-@module
+@myhdl.module
 def rom3(dout, addr, clk):
 
 
@@ -47,7 +48,7 @@ def rom3(dout, addr, clk):
 
     return rdLogic
 
-@module
+@myhdl.module
 def rom4(dout, addr, clk):
 
     @always_comb
@@ -57,7 +58,7 @@ def rom4(dout, addr, clk):
     return read
 
       
-@module
+@myhdl.module
 def RomBench(rom):
 
     dout = Signal(intbv(0)[8:])

myhdl/test/conversion/general/test_set_dir.py

@@ -1,5 +1,6 @@
 import os
 
+import myhdl
 from myhdl import *
 from tempfile import mkdtemp
 from shutil import rmtree
@@ -8,7 +9,7 @@ import myhdl
 _version = myhdl.__version__.replace('.','')
 _shortversion = _version.replace('dev','')
 
-@module
+@myhdl.module
 def simple_dir_model(din, dout, clk):
     """ Simple convertible model """
 

myhdl/test/conversion/general/test_ternary.py

@@ -3,9 +3,10 @@ import os
 path = os.path
 import unittest
 
+import myhdl
 from myhdl import *
 
-@module
+@myhdl.module
 def ternary1(dout, clk, rst):
 
     @always(clk.posedge, rst.negedge)
@@ -18,7 +19,7 @@ def ternary1(dout, clk, rst):
     return logic
 
 
-@module
+@myhdl.module
 def ternary2(dout, clk, rst):
 
     dout_d = Signal(intbv(0)[len(dout):])
@@ -36,7 +37,7 @@ def ternary2(dout, clk, rst):
 
     return logic, comb
 
-@module
+@myhdl.module
 def TernaryBench(ternary):
 
     dout = Signal(intbv(0)[8:])

myhdl/test/conversion/general/test_toplevel_method.py

@@ -1,5 +1,6 @@
 from __future__ import absolute_import
 import sys
+import myhdl
 from myhdl import *
 from myhdl import ConversionError
 from myhdl.conversion._misc import _error
@@ -9,7 +10,7 @@ class HdlObj(object):
     def __init__(self):
         pass
 
-    @module
+    @myhdl.module
     def method_func(self, clk, srst, x, y):
         z = Signal(intbv(0, min=y.min, max=y.max))
         ifx = self._mfunc(x, z)
@@ -22,14 +23,14 @@ class HdlObj(object):
 
         return hdl, ifx
 
-    @module
+    @myhdl.module
     def _mfunc(self, x, y):
         @always_comb
         def _hdl():
             y.next = x + 1
         return _hdl
 
-@module
+@myhdl.module
 def _func(x,y):
     @always_comb
     def _hdl():
@@ -40,7 +41,7 @@ class HdlObjObj(object):
     def __init__(self):
         pass
     
-    @module
+    @myhdl.module
     def method_func(self, clk, srst, x, y):
         z1 = Signal(intbv(0, min=y.min, max=y.max))
         z2 = Signal(intbv(0, min=y.min, max=y.max))
@@ -61,7 +62,7 @@ class HdlObjAttrSimple(object):
     def __init__(self):
         self.Constant = 3
 
-    @module
+    @myhdl.module
     def method_func(self, clk, srst, x, y):
         
         # limitation for class method conversion, the object attributes
@@ -81,7 +82,7 @@ class HdlObjNotSelf(object):
     def __init__(this):
         pass
 
-    @module
+    @myhdl.module
     def method_func(this, clk, srst, x, y):
 
         @always(clk.posedge)

myhdl/test/conversion/toVHDL/test_custom.py

@@ -6,6 +6,7 @@ import random
 from random import randrange
 random.seed(2)
 
+import myhdl
 from myhdl import *
 
 from myhdl import ConversionError
@@ -14,7 +15,7 @@ from myhdl.conversion._misc import _error
 
 ACTIVE_LOW, INACTIVE_HIGH = 0, 1
 
-@module
+@myhdl.module
 def incRef(count, enable, clock, reset, n):
     """ Incrementer with enable.
     
@@ -36,7 +37,7 @@ def incRef(count, enable, clock, reset, n):
     return logic
 
 
-@module
+@myhdl.module
 def incGen(count, enable, clock, reset, n):
     """ Generator with vhdl_code is not permitted """
     @instance
@@ -52,7 +53,7 @@ def incGen(count, enable, clock, reset, n):
     return logic
 
                                         
-@module
+@myhdl.module
 def inc(count, enable, clock, reset, n):
     """ Incrementer with enable.
     
@@ -91,7 +92,7 @@ end process;
 
 
 
-@module
+@myhdl.module
 def incErr(count, enable, clock, reset, n):
     
     @always(clock.posedge, reset.negedge)
@@ -124,7 +125,7 @@ end
 
 
 
-@module
+@myhdl.module
 def inc_comb(nextCount, count, n):
 
     @always_comb
@@ -142,7 +143,7 @@ $nextCount <= ($count + 1) mod $n;
 
     return logic
 
-@module
+@myhdl.module
 def inc_seq(count, nextCount, enable, clock, reset):
 
     @always(clock.posedge, reset.negedge)
@@ -172,7 +173,7 @@ end process;
     
     return logic
 
-@module
+@myhdl.module
 def inc2(count, enable, clock, reset, n):
     
     nextCount = Signal(intbv(0, min=0, max=n))
@@ -183,13 +184,13 @@ def inc2(count, enable, clock, reset, n):
     return comb, seq
 
 
-@module
+@myhdl.module
 def inc3(count, enable, clock, reset, n):
     inc2_inst = inc2(count, enable, clock, reset, n)
     return inc2_inst
 
 
-@module
+@myhdl.module
 def clockGen(clock):
     @instance
     def logic():
@@ -203,7 +204,7 @@ NRTESTS = 1000
 
 ENABLES = tuple([min(1, randrange(5)) for i in range(NRTESTS)])
 
-@module
+@myhdl.module
 def stimulus(enable, clock, reset):
     @instance
     def logic():
@@ -222,7 +223,7 @@ def stimulus(enable, clock, reset):
     return logic
 
 
-@module
+@myhdl.module
 def check(count, enable, clock, reset, n):
     @instance
     def logic():
@@ -240,7 +241,7 @@ def check(count, enable, clock, reset, n):
             print(count)
     return logic
 
-@module
+@myhdl.module
 def customBench(inc):
 
     m = 8