From db012cc557e337137683753eb0e665ba19c39e6e Mon Sep 17 00:00:00 2001
From: Jan Decaluwe <jan@jandecaluwe.com>
Date: Fri, 8 Oct 2010 18:21:45 +0200
Subject: [PATCH] Better handling of mapping to case in VHDL use others clause
 when possible, only convert to case when it's a full case

---
 myhdl/conversion/_analyze.py |  2 +-
 myhdl/conversion/_toVHDL.py  | 20 ++++++++++++++------
 2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/myhdl/conversion/_analyze.py b/myhdl/conversion/_analyze.py
index de172c6c..2f31cdf9 100644
--- a/myhdl/conversion/_analyze.py
+++ b/myhdl/conversion/_analyze.py
@@ -1103,7 +1103,7 @@ class _AnalyzeVisitor(ast.NodeVisitor, _ConversionMixin):
         node.isCase = True
         node.caseVar = var1
         node.caseItem = item1
-        if (len(choices) == _getNritems(var1.obj)) or (node.else_ is not None):
+        if (len(choices) == _getNritems(var1.obj)) or node.else_:
             node.isFullCase = True
 
 
diff --git a/myhdl/conversion/_toVHDL.py b/myhdl/conversion/_toVHDL.py
index 117fa25a..4d46e1be 100644
--- a/myhdl/conversion/_toVHDL.py
+++ b/myhdl/conversion/_toVHDL.py
@@ -1614,7 +1614,8 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
     def visit_If(self, node):
         if node.ignore:
             return
-        if node.isCase:
+        # only map to VHDL case if it's a full case
+        if node.isFullCase:
             self.mapToCase(node)
         else:
             self.mapToIf(node)
@@ -1653,15 +1654,22 @@ class _ConvertVisitor(ast.NodeVisitor, _ConversionMixin):
         self.visit(var)
         self.write(" is")
         self.indent()
-        for test, suite in node.tests:
+        for i, (test, suite) in enumerate(node.tests):
             self.writeline()
             item = test.case[1]
-            self.write("when ")
             if isinstance(item, EnumItemType):
-                self.write(item._toVHDL())
+                itemRepr = item._toVHDL()
             else:
-                self.write(self.BitRepr(item, obj))
-            self.write(" =>")
+                itemRepr = self.BitRepr(item, obj)
+            comment = ""
+            # potentially use default clause for last test
+            if (i == len(node.tests)-1) and not node.else_:
+                self.write("when others")
+                comment = " -- %s" % itemRepr
+            else:       
+                self.write("when ")
+                self.write(itemRepr)
+            self.write(" =>%s" % comment)
             self.indent()
             self.visit_stmt(suite)
             self.dedent()